Static random access memory device having a high speed read-out and precharging arrangement

Claim 1

A semiconductor memory device where in a plurality of memory cells are provided between a pair of bit lines, and are controlled via a word line and a precharging line, wherein the memory device comprises for each memory cell: a pair of access transistors each formed from a MOS transistor of a first conductivity type channel, the memory cell being connected in series between the pair of access transistors between the pair of bit lines, each access transistor being connected to be selectively controlled by the word line; a pair of MOS transistors of the first conductivity type channel each connected at the gate and drain thereof to an external voltage supply and at the source thereof to a separate one of the bit lines to act as first variable loads; and a pair of MOS transistors of a second conductivity type channel each connected at its source to the external voltage supply and at its drain to a separate one of the bit lines to individually terminate the bit line for performing a precharging operation before selection of the word line.