Low voltage inhibit control apparatus

Claim 2

In conjuction with a microprocessor system having a power supply, low voltage inhibit control apparatus comprising: a low voltage inhibit circuit coupled to the power supply for sensing when the power supply output becomes below a predetermined voltage and supplying a power down reset signal in response thereto; and control circuitry coupled so as to receive the power down reset signal from said low voltage inhibit circuit and further coupled so as to receive a first instruction signal from the microprocessor system, for preventing the received power down reset signals from being supplied to the microprocessor system in response to receiving the first instruction signal and allowing the received power down reset signals to be supplied to the microprocessor system when lacking the first instruction signal.

Claim 3

In conjuction with a microprocessor system having a power supply, low voltage inhibit control apparatus as claimed in claim 1, wherein the first instruction signal is a data signal.

Claim 4

In conjunction with a microprocessor system having a power supply, low voltage inhibit control apparatus as claimed in claim 1, wherein the control circuitry comprises a gate including, a first input terminal connected to receive the power down reset signals, a second input terminal connected to receive the first instruction signal applied thereto, and an output terminal connected to supply the power down reset signals to the microprocessor system when lacking the first instruction signal to said second input terminal.

Claim 5

In conjunction with a microprocessor system having a power supply, low voltage inhibit control apparatus comprising: a low voltage inhibit circuit coupled to the power supply for sensing when the power supply output becomes below a predetermined voltage and supplying a power down reset signal in response thereto; and control circuitry coupled so as to receive the power down reset signal from said low voltage inhibit circuit and further coupled so as to receive a first and second instruction signal from the microprocessor system, for preventing the received power down reset signals from being supplied to the microprocessor system in response to receiving the first and second instruction signals and allowing the received power down reset signals to be supplied to the microprocessor system when at least one of the first and second instruction signals.

Claim 6

In conjunction with a microprocessor system having a power supply, low voltage inhibit control apparatus comprising: a low voltage inhibit circuit coupled to the power supply for sensing when the power supply output becomes below a predetermined voltage and supplying a power down reset signal in response thereto; and control circuitry coupled so as to receive the power down reset signal from said low voltage inhibit circuit and further coupled so as to receive a first and second instruction signal from the microprocessor system, for preventing the received power down reset signals from being supplied to the microprocessor system in response to receiving the first and second instruction signals and allowing the received power down reset signals to be supplied to the microprocessor system when at least one of the first and second instruction signals.

Claim 7

In conjunction with a microprocessor system having a power supply, low voltage inhibit control apparatus as claimed in claim 4, wherein the first instruction signal is a data signal, and the second instruction signal is a write signal.

Claim 8

In conjunction with a microprocessor system having a power supply, low voltage inhibit control apparatus as claimed in claim 5, wherein the control circuitry further comprises, a state memory circuit having a first and second state, an initial state setting circuit coupled to the power supply and to said state memory circuit, for setting the initial state of said state memory circuit to the first state when the power supply is turned on, a state inversion control circuit coupled to said state memory circuit and further coupled so as to receive the data signal and the write signal from the microprocessor system, for determining the state of said state memory circuit in accordance with the received data and write signals, and gate means coupled to receive the power down reset signal and further coupled to the state memory circuit, for allowing the received power down reset signals to be supplied to the microprocessor system in response to the first state of the state memory circuit and preventing the received power down reset signals from being supplied to the microprocessor system in response to the second state of the state memory circuit.

Claim 9

In conjunction with a microprocessor system having a power supply, low voltage inhibit control apparatus as claimed in claim 6, wherein said state inversion control circuit sets the state of the state memory circuit to the second state in response to receiving the data and write signals.

Claim 10

In conjunction with a microprocessor system having a power supply and a low voltage inhibit circuit, a method of controlling the reset of the microprocessor system in accordance with first and second instruction signals supplied by the microprocessor system, comprising the steps of: sensing by the low voltage inhibit circuit when the power supply output becomes below a predetermined voltage and supplying a power down reset signal in response thereto; receiving the power down reset signal from said low voltage inhibit circuit and receiving the first and second instruction signals from the microprocessor system; and allowing the received power down reset signals to be supplied to the microprocessor system in response to a first mode of the first and second instruction signals, and preventing the received power down reset signals from being supplied to the microprocessor system in response to a second mode of the first and second instruction signals.

Claim 11

In conjunction with a microprocessor system having a power supply and a low voltage inhibit circuit, a method of controlling the reset of the microprocessor system in accordance with first and second instruction signals supplied by the microprocessor system, comprising the steps of: sensing by the low voltage inhibit circuit when the power supply output becomes below a predetermined voltage and supplying a power down reset signal in response thereto; receiving the power down reset signal from said low voltage inhibit circuit and receiving the first and second instruction signals from the microprocessor system; and allowing the received power down reset signals to be supplied to the microprocessor system in response to a first mode of the first and second instruction signals, and preventing the received power down reset signals from being supplied to the microprocessor system in response to a second mode of the first and second instruction signals.