Prevention of parasitic mechanisms in junction isolated devices

Claim 3

The device of claim 1, wherein said semiconductor device is an integrated circuit chip.

Claim 4

The device of claim 1, wherein said semiconductor device is a discrete semiconductor device.

Claim 5

The device of claim 1, wherein said isolation biasing element comprises an active transistor device having: a first load terminal connected to said isolation; a second load terminal connected to an external connection; and a control terminal for receiving a control signal for turning on said active transistor device.

Claim 6

Means for preventing parasitic forward biasing of isolation junctions between isolation regions and active devices in a semiconductor device comprising: a first biasing means having a first load terminal connected to ground potential; a second load terminal connected to the isolation region of said isolation junction, and a control terminal; and a second biasing means having a first load terminal connected to an external connection of said semiconductor device, a second load terminal connected to said isolation region, a control terminal connected to said control terminal of said first biasing mans, said control terminals receiving a control signal, said first biasing means biasing said isolation region to said round potential when said ground potential is lower than a potential at said external connection, and said second biasing means biasing said isolation to the potential at said external connection when said potential is lower than said ground potential.

Claim 7

Means for preventing parasitic forward biasing of isolation junctions between isolation regions and active devices in a semiconductor device comprising: a first biasing means having a first load terminal connected to ground potential; a second load terminal connected to the isolation region of said isolation junction, and a control terminal; and a second biasing means having a first load terminal connected to an external connection of said semiconductor device, a second load terminal connected to said isolation region, a control terminal connected to said control terminal of said first biasing mans, said control terminals receiving a control signal, said first biasing means biasing said isolation region to said round potential when said ground potential is lower than a potential at said external connection, and said second biasing means biasing said isolation to the potential at said external connection when said potential is lower than said ground potential.

Claim 8

The means of claim 5, wherein said isolation junction comprises an epitaxial-tank/substrate-junction wherein said 10 substrate is the isolation region.

Claim 9

The means of claim 5, wherein said isolation junction comprises an epitaxial-tank/isolation-region junction wherein said isolation region provides the isolation.

Claim 10

The means of claim 6, wherein said epitaxial-tank is N-type semiconductor material and said substrate is P-type semiconductor material.

Claim 11

The means of claim 6, wherein said epitaxial-tank is P-type semiconductor material and said substrate is N-type semiconductor material.

Claim 12

The means of claim 7, wherein said epitaxial-tank is N-type semiconductor material and said isolation region is P-type semiconductor material.

Claim 13

The means of claim 7, wherein said epitaxial-tank is P-type semiconductor material and said isolation region is N-type semiconductor material.

Claim 14

Means for preventing parasitic forward biasing of a semiconductor PN junction of a junction isolated semiconductor device comprising: a biasing element for reducing a voltage potential of said PN junction to a level below a forward biasing potential, said biasing element including means for diverting current away from said junction, said biasing element further having a control terminal for receiving a control signal for turning on said biasing element.

Claim 15

Means for preventing parasitic forward biasing of a semiconductor PN junction of a junction isolated semiconductor device comprising: a biasing element for reducing a voltage potential of said PN junction to a level below a forward biasing potential, said biasing element including means for diverting current away from said junction, said biasing element further having a control terminal for receiving a control signal for turning on said biasing element.

Claim 16

The means of claim 12 wherein said biasing element comprises: an active transistor device having, an output terminal connected to one side of said PN junction, at least one low potential terminal connected to the opposite side of said PN junction, a control terminal for receiving bias input for turning on said biasing element to provide an output voltage at said output terminal.

Claim 17

The means of claim 13, wherein said biasing element is a field effect device, said output terminal is a source said low potential terminal is a drain, and said control terminal is a gate.

Claim 18

The means of claim 13, wherein said biasing element is a bipolar device, said output terminal is a collector, said low potential terminal is an emitter, and said control terminal is a base.

Claim 19

The means of claim 12, wherein said semiconductor device is an integrated circuit device including bipolar and field effect devices.

Claim 20

The device of claim 4 wherein said external connection is connected to a voltage potential.

Claim 21

The means of claim 4, wherein said active transistor device further includes a third load terminal connected to ground.

Claim 24

The device of claim 19, wherein said multi-epitaxial layer device includes a first epitaxial layer having a dopant type different from a second epitaxial layer dopant type, said first epitaxial layer including isolation regions of said second dopant type for separating said epitaxial layer into at least two biasing zones corresponding to said first and second biasing elements, said isolation regions being biased to a fixed potential.

Claim 27

The device of claim 1, wherein said semiconductor device includes circuitry for providing reverse supply protection for said semiconductor devices.

Claim 28

The device of claim 19, wherein said semiconductor device includes circuitry for providing reverse supply protection for said semiconductor devices.

Claim 29

The device of claim 1, wherein said junction isolated devices are formed including multi-epitaxial layers.