US5051865A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Multi-layer semiconductor device
Assignee: Fujitsu Ltd
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Filing: 1991-03-11
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Granted: 1991-09-24
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Expires: 2011-03-11
Abstract
Abstract A multi-layer semiconductor device which includes a stacked wafer body having a plurality of sets of two semiconductor wafers and a heat sink plate interposed therebetween. An end of the heat sink plate of each set of wafers is exposed at at least one of the side surfaces of the stacked wafer body. An intermediate connecting circuit is provided for connecting circuits in each of the sets of two semiconductors wafers, the intermediate connecting circuit is provided on at least one side surface other than the surface at which the ends of the heat sink plate are exposed.
Inventors
- 👤 Takashi Kato
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 13:34
CPC Classifications
H; H10; H10W; H10W40/00; H10W40/10; H10W90/00; H10W70/00; H10W70/60; H10W70/67; H10W70/68; H10W70/682; H10W72/00; H10W72/01; H10W72/50; H10W72/541; H10W72/5449; H10W72/551; H10W72/552; H10W72/5524; H10W72/834; H10W90/20; H10W90/288; H10W90/701; H10W90/751; H10W90/754
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
216 words
A multi-layer semiconductor device comprising: a stacked wafer body having polished vertically sliced side surfaces, including: a plurality of sets of two semiconductor wafers having an integrated element formed on each of said semiconductor wafers; an insulating layer formed on said semiconductor wafer; transistors directly formed on exposed semiconductor wafers in one of the polished vertically sliced side surfaces of said stacked wafer body for controlling the response of said integrated element on each of said semiconductor wafers; and a plurality of heat sink plates formed between and contacting said sets of two semiconductor wafers, one back side of each of said semiconductor wafers being formed on and having its entire surface in contact with said heat sink plates, an element-formed side of each of said semiconductor wafers having said insulating layer formed thereon, an end of said heat sink plate of each of said sets of two semiconductor wafers being exposed and projecting from at least one of said surfaces of said stacked wafer body; and an intermediate connecting circuit, connected to said stacked wafer body, for connecting circuits in each of said sets or two semiconductor wafers, said intermediate connecting circuit being provided on at least one side surface other than the surface at which the ends of said heat sink plates are exposed.
Claim 2
Dependent Claim
216 words
A multi-layer semiconductor device comprising: a stacked wafer body having polished vertically sliced side surfaces, including: a plurality of sets of two semiconductor wafers having an integrated element formed on each of said semiconductor wafers; an insulating layer formed on said semiconductor wafer; transistors directly formed on exposed semiconductor wafers in one of the polished vertically sliced side surfaces of said stacked wafer body for controlling the response of said integrated element on each of said semiconductor wafers; and a plurality of heat sink plates formed between and contacting said sets of two semiconductor wafers, one back side of each of said semiconductor wafers being formed on and having its entire surface in contact with said heat sink plates, an element-formed side of each of said semiconductor wafers having said insulating layer formed thereon, an end of said heat sink plate of each of said sets of two semiconductor wafers being exposed and projecting from at least one of said surfaces of said stacked wafer body; and an intermediate connecting circuit, connected to said stacked wafer body, for connecting circuits in each of said sets or two semiconductor wafers, said intermediate connecting circuit being provided on at least one side surface other than the surface at which the ends of said heat sink plates are exposed.
Claim 3
Dependent Claim
19 words
A multi-layer semiconductor device according to claim 1, wherein said heat sink plate comprises one of aluminum and copper.
Claim 4
Dependent Claim
39 words
A multi-layer semiconductor device according to claim 2, wherein the thickness of said aluminum heat sink plate is approximately 70 μm or more, and wherein the thickness of said copper heat sink plate is approximately 42 μm or more.
Claim 5
Dependent Claim
37 words
A multi-layer semiconductor device according to claim 1, further including a heat sink, wherein said heat sink plates have exposed ends, and wherein said exposed ends of said heat sink plates are connected to said heat sink.
Claim 6
Dependent Claim
61 words
A multi-layer semiconductor device according to claim 4, wherein said heat sink plates have extended ends, wherein said heat sink has grooves formed therein, and wherein said connection of said exposed ends of said heat sink plates to said heat sink is carried out by connecting said extended ends of said heat sink plates to said grooves of said heat sink.
Claim 7
Dependent Claim
71 words
A multi-layer semiconductor device according to claim 4, wherein the exposed ends of said heat sink plates are fixed at right angles to said heat sink plates, wherein said intermediate connecting circuit being further provided on an opposite side surface from said side surface from which the ends of said heat sink plates project and further includes bonding pads, and wherein said semiconductor device is assembled in a three-dimensional IC package.
Claim 8
Dependent Claim
41 words
A multi-layer semiconductor device according to claim 1, wherein one of the side surfaces from which the end of said heat sink plate projects is the back side of the other side surface on which said intermediate connecting circuit is formed.
Claim 9
Dependent Claim
20 words
A multi-layer semiconductor device according to claim 7, wherein said intermediate connecting circuit has electrodes embedded in said semiconductor wafers.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-09-23 | 1995-03-25 | 1995-09-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-09-23 | 1999-03-25 | 1999-09-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-09-23 | 2003-03-25 | 2003-09-24 | $7700.00 | Window Closed / Lapsed |