Digital autozero circuit operable in a plurality of modes with separate storage for offset corrections for each mode

Claim 2

An autozero compensator in combination with a data conversion circuit, operable in a plurality of modes, for digitizing an analog signal as a function of the sum of said analog input signal and one of a plurality of different first analog offset signal provided respectively for each of said modes, said compensator comprising, in combination, means for generating a plurality of desired digital offset signals, each corresponding to one of said modes; signal comparison means for periodically comparing each of said desired offset signals with the output of said conversion circuit so as to generate a like plurality of digital corrections signals, said conversion circuit being set to operating in a corresponding one of said modes and having its input connected to system ground; means for storing said digital correction signals; means for periodically updating each of said digital correction signals stored in said signal storage means in response to the period comparison of said desired offset signals to said output of said conversion circuit; digital-to-analog converter means for converting each of said stored digital signals to a corresponding autozero analog signal as a function of the corresponding operating mode; and means for altering said sum responsively to each of said autozero analog signals so as to autozero said conversion circuit for each of said corresponding modes.

Claim 3

An autozero compensator according to claim 1, wherein said data conversion circuit includes an analog input for receiving said analog input signal, a digital output for providing a digital output signal as a function of said sum, means for selecting the operating mode of said circuit, and means for generating said analog offset signals in accordance with the respective operating mode selected; and wherein said means for periodically updating each of said digital correction signals includes means for coupling said analog input to system ground, said means for generating said desired digital offset signals provides respectively predetermined values of each of said digital offset signals for each of said operating modes; and said signal comparison means includes means for generating comparison signals as a function of the relative magnitudes of each of said desired digital offset signals compared with the digital output signal of said circuit when said analog input is coupled to system ground and the corresponding analog offset signal is generated for each of said operating modes, and said means for periodically updating each of said digital correction signals is responsive to a function of said difference signal.

Claim 4

An autozero compensator according to claim 2, wherein said means for selecting the operating mode of said circuit selects said operating mode in accordance with a predetermined sequence.

Claim 5

In a data conversion circuit operable in a plurality of modes and comprising an input for receiving an analog input signal, an analog-to-digital converter for digitizing said analog signal as a function of the sum of said analog input signal and one of a plurality of different first analog offset signals provided respectively for each of said modes, means for detecting the level of said analog input signal, a programmable gain amplifier having its output coupled to the input of said converter, and means for setting the gain of said amplifier at one of at least two gain settings as a function of the detected level of said analog input signal so that said amplifier is set for maximum gain for the detected level of said analog input signal such that said amplifier will not over-range said converter and the response of said amplifier is substantially linear throughout the dynamic range of said amplifier at said gain settings, said circuit further comprising: means for generating a plurality of desired digital offset signals, each corresponding to one of said modes; means for comparing said desired offset signals with the output of said conversion circuit having its input grounded so as to generate a like plurality of digital correction signals; means for storing said digital correction signals; means for periodically updating each of said digital correction signals stored in said signal storage means; digital-to-analog converter means for converting each of said stored digital signals to an autozero analog signal as a function of said operating mode; and means for altering said sum responsively to said autozero analog signal so as to autozero said conversion circuit for each of said operating modes.

Claim 6

In a data conversion circuit operable in a plurality of modes and comprising an input for receiving an analog input signal, an analog-to-digital converter for digitizing said analog signal as a function of the sum of said analog input signal and one of a plurality of different first analog offset signals provided respectively for each of said modes, means for detecting the level of said analog input signal, a programmable gain amplifier having its output coupled to the input of said converter, and means for setting the gain of said amplifier at one of at least two gain settings as a function of the detected level of said analog input signal so that said amplifier is set for maximum gain for the detected level of said analog input signal such that said amplifier will not over-range said converter and the response of said amplifier is substantially linear throughout the dynamic range of said amplifier at said gain settings, said circuit further comprising: means for generating a plurality of desired digital offset signals, each corresponding to one of said modes; means for comparing said desired offset signals with the output of said conversion circuit having its input grounded so as to generate a like plurality of digital correction signals; means for storing said digital correction signals; means for periodically updating each of said digital correction signals stored in said signal storage means; digital-to-analog converter means for converting each of said stored digital signals to an autozero analog signal as a function of said operating mode; and means for altering said sum responsively to said autozero analog signal so as to autozero said conversion circuit for each of said operating modes.

Claim 7

An autozero compensator according to claim 4, wherein said means for selecting the gain setting of said amplifier selects said gain setting in accordance with a predetermined sequence.

Claim 8

A circuit according to claim 4, wherein said signal storage means comprises a plurality of digital counters, one for each of said gain settings of amplifier, and connected so as to be responsive to said means for updating.

Claim 9

A circuit according to claim 6, including controller means coupled to said means for comparing and to each of said plurality of counters, for enabling the counter corresponding to the gain setting of said amplifier when said corresponding counter is updated by said means for updating said digital correction signal, so that said corresponding counter is incremented so as to increase the magnitude of said digital correction signal responsively to said comparator means when said desired digital offset signal is greater than said digital output signal of said data conversion circuit and is decremented so as to decrease the magnitude of said digital correction signal responsively to said comparator means when said desired digital offset signal is less than said digital output signal of said data conversion circuit.

Claim 10

A circuit according to claim 6, wherein each of said counters contain a predetermined number of stages for storing each of said digital correction signals as a predetermined number of bits, wherein said means for converting each of said stored digital signals to an autozero analog signal includes means for using fewer than said predetermined number of stages of the corresponding counter so as to provide a predetermined number of most significant bits of said digital signal stored in said corresponding counter and minimize noise effects on the count stored in each of said counters.