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US5057902A
Expired / Lapsed
US
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Self-aligned semiconductor devices
Assignee: GlobalFoundries Inc
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Filing: 1989-05-11
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Granted: 1991-10-15
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Expires: 2009-05-11
Abstract
Abstract A novel process is provided for fabricating transistors (14), contacts (46s, 40g, 46d) and interconnections (46c) in a novel self-aligned configuration. The process of the invention permits higher packing densities, and allows feature distances to approach 0.5 μm and lower. In a preferred embodiment, the configuration is also planarized. A unique combination of masks in conjunction with a multi-layer structure (28) formed on the surface of a semiconductor wafer (16), the multi-layer structure including a buried etch-stop layer therein (28b), defined the source (18), gate (22), and drain (20) elements and their geometry relative to each to each and to interconnects. Polysilicon plug (40, 46) contacts through slots in the multi-structure layer permit vertical contact to be made to the various elements. Silicidation (56) of the polysilicon plugs reduces series resistance in the vertical direction and permits strapping of N + and P + polysilicon plugs.
Inventors
- 👤 Jacob D. Haskell
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 16:54
CPC Classifications
H; H10; H10D; H10D64/00; H10D64/01; H10D64/011; H10D64/0111; H10D64/0113; H10W; H10W20/00; H10W20/01; H10W20/031; H10W20/056; H10W20/40; H10W20/41; H10W20/42
Claims Analysis
Total Claims: 21
Claim 1
Independent Claim
226 words
A field effect transistor comprising source, drain, and gate regions formed in a major surface of a semiconductor substrate, said semiconductor substrate provided with (1) source and drain contacts to said source and drain regions, respectively, and (2) a gate electrode overlying a gate oxide overlying said gate region, characterized by (a) said source, gate, and drain contacts comprising vertically-disposed plugs comprising a conducting material, disposed in openings formed in insulating material formed on said substrate, said openings defined by substantially perpendicular walls, said conducting material contacting said semiconductor surface in the case of said source and drain contacts and contacting said gate oxide in the case of said gate contact, at least some of which plugs terminate to form a coplanar surface in an area above said substrate surface and substantially parallel to said substrate, at least one of said plugs contacted by a planar contact; (b) at least two of said plurality of plugs having a similar lateral dimension in at least one direction parallel to said substrate at said major surface; and (c) said insulating layer comprising a multilayer structure comprising (1) a first layer consisting essentially of an oxide, (2) a second layer consisting essentially of an etch-stop material having a significantly different etch rate than said oxide of said first layer, and (3) a third layer consisting essentially of an oxide.
Claim 2
Dependent Claim
226 words
A field effect transistor comprising source, drain, and gate regions formed in a major surface of a semiconductor substrate, said semiconductor substrate provided with (1) source and drain contacts to said source and drain regions, respectively, and (2) a gate electrode overlying a gate oxide overlying said gate region, characterized by (a) said source, gate, and drain contacts comprising vertically-disposed plugs comprising a conducting material, disposed in openings formed in insulating material formed on said substrate, said openings defined by substantially perpendicular walls, said conducting material contacting said semiconductor surface in the case of said source and drain contacts and contacting said gate oxide in the case of said gate contact, at least some of which plugs terminate to form a coplanar surface in an area above said substrate surface and substantially parallel to said substrate, at least one of said plugs contacted by a planar contact; (b) at least two of said plurality of plugs having a similar lateral dimension in at least one direction parallel to said substrate at said major surface; and (c) said insulating layer comprising a multilayer structure comprising (1) a first layer consisting essentially of an oxide, (2) a second layer consisting essentially of an etch-stop material having a significantly different etch rate than said oxide of said first layer, and (3) a third layer consisting essentially of an oxide.
Claim 3
Dependent Claim
14 words
The transistor of claim 1 wherein said conducting material comprises doped or undoped polysilicon.
Claim 4
Dependent Claim
24 words
The transistor of claim 2 wherein said doped polysilicon material is selected from the group consisting of N + and P + doped material.
Claim 5
Dependent Claim
24 words
The transistor of claim 2 wherein at least some of said polysilicon plugs include a silicided outer layer to control vertical series resistance thereof.
Claim 6
Dependent Claim
24 words
The transistor of claim 4 wherein N + and P + polysilicon plugs are shunted together by said silicide to form an ohmic interconnect.
Claim 7
Dependent Claim
34 words
The transistor of claim 4 wherein said source and drain regions are contacted by said polysilicon plugs, said polysilicon plugs including said silicided outer layer to control the vertical series resistance of said plugs.
Claim 8
Dependent Claim
36 words
The contacts of claim 1 wherein said semiconductor substrate comprises silicon, said first layer consists essentially of silicon dioxide, said second layer consists essentially of silicon nitride, and said third layer consists essentially of silicon dioxide.
Claim 9
Dependent Claim
17 words
The contacts of claim 7 wherein said first layer of silicon dioxide is about 2,500 Å thick.
Claim 10
Dependent Claim
17 words
The contacts of claim 7 wherein said first layer of silicon dioxide is about 400 Å thick.
Claim 11
Dependent Claim
47 words
The field effect transistor of claim 1 wherein at least one of said plugs is connected by a planar interconnect on a plane, which is above said semiconductor substrate and which is below said planar contact, to at least one plug of a neighboring field effect transistor.
Claim 12
Dependent Claim
233 words
A CMOS device comprising source, drain, and gate regions formed in a major surface of a semiconductor substrate, said semiconductor substrate provided with (1) source and drain contacts to said source and drain regions, respectively, and (2) a gate electrode overlying a gate oxide overlying said gate region, characterized by (a) said source, gate, and drain contacts comprising vertically-disposed plugs comprising a conducting material, disposed in openings formed in insulating material formed on said substrate, said openings defined by substantially perpendicular walls, said conducting material contacting said semiconductor surface in the case of said source and drain contacts and contacting said gate oxide in the case of said gate contact, at least some of which plugs terminate to form a coplanar surface in an area above said substrate surface and substantially parallel to said substrate, at least one of said plugs contacted by a planar contact; (b) at least two of said plurality of plugs having a similar lateral dimension in at least one direction parallel to said substrate at said major surface; and (c) said insulating layer comprising a multilayer structure comprising said insulating layer comprising a multilayer structure comprising (1) a first layer consisting essentially of an oxide, (2) a second layer consisting essentially of an etch-stop material having a significantly different etch rate than said oxide of said first layer, and (3) a third layer consisting essentially of an oxide.
Claim 13
Dependent Claim
233 words
A CMOS device comprising source, drain, and gate regions formed in a major surface of a semiconductor substrate, said semiconductor substrate provided with (1) source and drain contacts to said source and drain regions, respectively, and (2) a gate electrode overlying a gate oxide overlying said gate region, characterized by (a) said source, gate, and drain contacts comprising vertically-disposed plugs comprising a conducting material, disposed in openings formed in insulating material formed on said substrate, said openings defined by substantially perpendicular walls, said conducting material contacting said semiconductor surface in the case of said source and drain contacts and contacting said gate oxide in the case of said gate contact, at least some of which plugs terminate to form a coplanar surface in an area above said substrate surface and substantially parallel to said substrate, at least one of said plugs contacted by a planar contact; (b) at least two of said plurality of plugs having a similar lateral dimension in at least one direction parallel to said substrate at said major surface; and (c) said insulating layer comprising a multilayer structure comprising said insulating layer comprising a multilayer structure comprising (1) a first layer consisting essentially of an oxide, (2) a second layer consisting essentially of an etch-stop material having a significantly different etch rate than said oxide of said first layer, and (3) a third layer consisting essentially of an oxide.
Claim 14
Dependent Claim
45 words
The CMOS device of claim 11 wherein at least one of said plugs is connected by a planar interconnect on a plane, which is above said semiconductor substrate and which is below said planar contact, to at least one plug of a neighboring CMOS device.
Claim 15
Dependent Claim
23 words
The device of claim 11 wherein said polysilicon material is selected from the group consisting of N + and P + doped material.
Claim 16
Dependent Claim
24 words
The device of claim 11 wherein at least some of said polysilicon plugs include a silicided outer layer to control vertical series resistance thereof.
Claim 17
Dependent Claim
24 words
The device of claim 14 wherein N + and P + polysilicon plugs are shunted together by said silicide to form an ohmic interconnect.
Claim 18
Dependent Claim
34 words
The device of claim 14 wherein said source and drain regions are contacted by said polysilicon plugs, said polysilicon plugs including said silicided outer layer to control the vertical series resistance of said plugs.
Claim 19
Dependent Claim
36 words
The contacts of claim 11 wherein said semiconductor substrate comprises silicon, said first layer consists essentially of silicon dioxide, said second layer consists essentially of silicon nitride, and said third layer consists essentially of silicon dioxide.
Claim 20
Dependent Claim
17 words
The contacts of claim 17 wherein said first layer of silicon dioxide is about 2,500 Å thick.
Claim 21
Dependent Claim
17 words
The contacts of claim 17 wherein said first layer of silicon dioxide is about 400 Å thick.
References Cited (Backward Citations)
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