US5065216A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor integrated circuit having interconnection with improved design flexibility, and method of production
Assignee: Fujitsu Ltd
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Filing: 1990-02-09
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Granted: 1991-11-12
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Expires: 2010-02-09
Abstract
Abstract A semiconductor integrated circuit comprises a substrate of a first semiconductor type doped by a first impurity element with a first impurity density, the first semiconductor type being one of p-type and n-type semiconductors, a conductive layer formed on a back surface of the substrate, a first layer of a second semiconductor type doped by a second impurity element different from the first impurity element and formed on a front surface of the substrate, the second semiconductor type being the other of the p-type and n-type semiconductors and the first layer having a second impurity density lower than the first impurity density, a second layer of the first semiconductor type formed on the first layer for forming circuit elements therein, a first region of the second semiconductor type extending from a top surface of the first layer and reaching a top surface of the second layer, and a second region of the first semiconductor type extending from a top surface of the substrate and reaching the top surface of said second layer, the first layer and the second region forming a conductive path for supplying a power source voltage to the circuit elements in the second layer from the back surface of the substrate.
Inventors
- 👤 Kouichi Suzuki
- 👤 Norihito Miyoshi
- 👤 Makoto Yoshida
- 👤 Masayuki Kokado
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 07:49
CPC Classifications
H; H10; H10D; H10D62/00; H10D62/10; H10D62/113; H10D62/114; H10D89/00; H10D89/60; H10D89/601; H10D89/711; H10D89/713; H10D62/115; H10D84/00; H10D84/60; H10D84/611; H10D84/613; H10W; H10W20/00; H10W20/40; H10W20/41; H10W20/43; H10W20/432; H10W72/00; H10W72/01; H10W72/019; H10W72/90; H10W70/00; H10W70/60; H10W70/67; H10W70/68; H10W70/682; H10W72/50; H10W72/541; H10W72/5445; H10W72/59; H10W72/931; H10W72/932; H10W72/951; H10W72/952; H10W90/00; H10W90/701; H10W90/751; H10W90/754
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
274 words
A semiconductor integrated circuit comprising: a substrate, having upper and lower main surfaces, of a first semiconductor type and doped with a first impurity element at a first impurity density, said first semiconductor type being one of p-type and n-type semiconductors; a conductive layer formed on the lower, main surface of said substrate; a first layer, having upper and lower surfaces, of a second semiconductor type doped with a second impurity element different from the first impurity element and formed on the upper, main surface of said substrate, said second semiconductor type being the other of the p-type and n-type semiconductor and said first layer having a second impurity density lower than the first impurity density; a second layer, having upper and lower surfaces, of the first semiconductor type formed on said first layer for forming circuit elements therein; a first region of the second semiconductor type surrounded by said second layer and extending from the upper surface of said first layer to the upper surface of said second layer, said first region forming a p-n junction with a part of the second layer that surrounds the first region; a second region of the first semiconductor type extending from the upper, main surface of said substrate to the upper surface of said second layer, said substrate and said second region forming a conductive path for supplying a power source voltage of a first predetermined voltage level to the circuit elements in said second layer from the lower, main surface of said substrate; and means for applying a voltage to the first region at a level such that the p-n junction is not forward biased.
Claim 2
Dependent Claim
274 words
A semiconductor integrated circuit comprising: a substrate, having upper and lower main surfaces, of a first semiconductor type and doped with a first impurity element at a first impurity density, said first semiconductor type being one of p-type and n-type semiconductors; a conductive layer formed on the lower, main surface of said substrate; a first layer, having upper and lower surfaces, of a second semiconductor type doped with a second impurity element different from the first impurity element and formed on the upper, main surface of said substrate, said second semiconductor type being the other of the p-type and n-type semiconductor and said first layer having a second impurity density lower than the first impurity density; a second layer, having upper and lower surfaces, of the first semiconductor type formed on said first layer for forming circuit elements therein; a first region of the second semiconductor type surrounded by said second layer and extending from the upper surface of said first layer to the upper surface of said second layer, said first region forming a p-n junction with a part of the second layer that surrounds the first region; a second region of the first semiconductor type extending from the upper, main surface of said substrate to the upper surface of said second layer, said substrate and said second region forming a conductive path for supplying a power source voltage of a first predetermined voltage level to the circuit elements in said second layer from the lower, main surface of said substrate; and means for applying a voltage to the first region at a level such that the p-n junction is not forward biased.
Claim 3
Dependent Claim
25 words
A semiconductor integrated circuit as claimed in claim 1 in which said first region has an impurity density higher than that of the first layer.
Claim 4
Dependent Claim
25 words
A semiconductor integrated circuit as claimed in claim 1 in which said second region has an impurity density approximately equal to that of the substrate.
Claim 5
Dependent Claim
21 words
A semiconductor integrated circuit as claimed in claim 1 in which said first region is surrounded laterally by an insulator layer.
Claim 6
Dependent Claim
21 words
A semiconductor integrated circuit as claimed in claim 1 in which said second region is surrounded laterally by an insulator layer.
Claim 7
Dependent Claim
83 words
A semiconductor integrated circuit as claimed in claim 1 wherein the means for applying a voltage comprises biasing means, connected to the first region at the upper surface of the second layer, for supplying thereto a second voltage of a second predetermined voltage level which maintains the p-n junction, said conductive layer being connectable to a power source voltage supply for applying a power source voltage of the first predetermined voltage level, as supplied thereby, to said lower, main surface of said substrate.
Claim 8
Dependent Claim
44 words
A semiconductor integrated circuit as claimed in claim 6 in which said first semiconductor type is the n-type, said second semiconductor type is the p-type, and said second predetermined voltage level is set to the lowest voltage level used in the semiconductor integrated circuit.
Claim 9
Dependent Claim
99 words
A semiconductor integrated circuit as claimed in claim 7 in which at least one said circuit element formed in the second layer comprises an npn transistor having an emitter, a base, and a collector, the semiconductor integrated circuit further comprising an interconnection structure disposed at the upper surface of the second layer for connecting the second region to the collector of the npn transistor so as to supply the power source voltage of the first predetermined voltage level, supplied to the second region from the power source voltage supply through the conductive layer and the substrate, to the collector.
Claim 10
Dependent Claim
56 words
A semiconductor integrated circuit as claimed in claim 6, in which said first semiconductor type is of the n-type and said second semiconductor type is of the p-type and said second predetermined voltage level, of said second voltage which is supplied to the first region by the biasing means, is lower than the first predetermined level.
Claim 11
Dependent Claim
44 words
A semiconductor integrated circuit as claimed in claim 6, in which said first semiconductor type is the p-type, said second semiconductor type is the n-type, and said second predetermined voltage level is set to the highest voltage level used in the semiconductor integrated circuit.
Claim 12
Dependent Claim
50 words
A semiconductor integrated circuit as claimed in claim 6, wherein the power source voltage of the first predetermined voltage level, supplied by the power source voltage supply, is the voltage V CC and the second voltage of the second predetermined voltage level is the power source voltage V EE .
Claim 13
Dependent Claim
54 words
A semiconductor integrated circuit as claimed in claim 1, wherein a second p-n junction is formed between the upper surface of the substrate and the lower surface of the first layer, and said means for applying a voltage generates a capacitance at the second p-n junction which absorbs fluctuations of the power source voltage.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-11-11 | 1995-05-13 | 1995-11-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-11-11 | 1999-05-13 | 1999-11-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-11-11 | 2003-05-13 | 2003-11-12 | $7700.00 | Window Closed / Lapsed |