US5067023A
Expired / Lapsed
US
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Image data coding apparatus
Assignee: Samsung Electronics Co Ltd
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Filing: 1990-06-28
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Granted: 1991-11-19
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Expires: 2010-06-28
Abstract
Abstract The image data coding apparatus of the present invention includes a First-In, First-Out memory, a pixel color discriminating section, black and white run length calculating sections, black and white code look-up tables, parallel input/serial output shift resisters, and a valid bit detecting section. The FIFO memory sequentially reads binary image data, and outputs them in the inputted order. The pixel color discriminating section discriminates the color of the pixels outputted from the FIFO memory. The black and white run length calculating sections calculate the run lengths of the pixels after the discriminations of the color of the pixels by the pixel color discriminating section. The code look-up table outputs the relevant codes in byte units after receipt of the code address from the black and white run length calculating sections. The parallel input/serial output shift register converts the parallel output data of the look-up table into serial data. The valid bit detecting section outputs parallel data in byte units after extracting only the valid bits among the serial data outputted from the parallel input/serial output shift register.
Inventors
- 👤 Eun J. Kim
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 18:29
CPC Classifications
H; H03; H03M; H03M1/00; H03M1/12; G; G06; G06T; G06T9/00; G06T9/005; H03M7/00; H03M7/30; H03M7/40; H04; H04N; H04N1/00; H04N1/41; H04N1/411; H04N1/413; H04N1/419
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
150 words
An image data coding apparatus for coding binary image data, comprising: a FIFO memory for sequentially reading binary image data, for outputting them in the inputted order; a pixel color discriminating section for discriminating the colors of the pixels outputted from said FIFO memory; black and white run length calculating sections for calculating the run lengths of the pixels of which color has been discriminated by said pixel color discriminating section; black and white code look-up tables for receiving the address of the code position corresponding to the pixel run lengths outputted from said black and white run length calculating sections; parallel input/serial output shift registers for shifting the parallel data outputted by said look-up tables into serial data form; and a valid bit detecting section for extracting only valid bits among serial data outputted from said parallel input/serial output shift register, and for generating parallel data in byte units.
Claim 2
Dependent Claim
150 words
An image data coding apparatus for coding binary image data, comprising: a FIFO memory for sequentially reading binary image data, for outputting them in the inputted order; a pixel color discriminating section for discriminating the colors of the pixels outputted from said FIFO memory; black and white run length calculating sections for calculating the run lengths of the pixels of which color has been discriminated by said pixel color discriminating section; black and white code look-up tables for receiving the address of the code position corresponding to the pixel run lengths outputted from said black and white run length calculating sections; parallel input/serial output shift registers for shifting the parallel data outputted by said look-up tables into serial data form; and a valid bit detecting section for extracting only valid bits among serial data outputted from said parallel input/serial output shift register, and for generating parallel data in byte units.
Claim 3
Dependent Claim
78 words
The image data coding apparatus as claimed in claim 1, wherein said black and white run length calculating sections respectively comrise two 6-bit counters for counting the number of the succeeding pixels outputted from said pixel color discriminating section; latches for latching the outputs of said 6-bit counters in synchronization with a master clock; and monostable multivibrators for supplying output enable control signals to said latches at the moment when the shifting of the pixel color is detected.
Claim 4
Dependent Claim
47 words
The image data coding apparatus as claimed in claim 1, wherein, from the lowest address of memory means of said code look-up tables, there are stored white pixel terminating codes, white pixel make-up codes, black pixel terminating codes, and black pixel make-up codes in the cited order.
Claim 5
Dependent Claim
210 words
The image data coding apparatus as claimed in claim 1, wherein said valid bit detecting section comprises a 4-bit downcounter for presetting the value of the valid bit length among the data outputted by said look-up tables, and for controlling the shifting operations of said parallel input/serial output shift register until said preset value becomes "zero", in order to extract only the valid bits among the output data of said parallel input/serial output shift register; a tristate buffer for transferring the master clock to the shift clock terminal of said parallel input/serial output shift register in accordance with the predetermined level of the signal supplied to its gate; a NAND gate for receiving the output of said 4-bit downcounter, and for generating control signals to be supplied to the gate of said tristate buffer; a serial input/parallel output shift register for converting the serial output data of said parallel input/serial output shift register into parallel data; and a modulo-8 counter for counting the number of the master clocks through said tristate buffer corresponding to the number of the valid bits, and for supplying to said serial input/parallel output shift register the output enable control signals which enables said serial input/parallel output shift register to output coded data in byte units.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-11-18 | 1995-05-20 | 1995-11-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-11-18 | 1999-05-20 | 1999-11-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-11-18 | 2003-05-20 | 2003-11-19 | $7700.00 | Window Closed / Lapsed |