US5070388A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Trench-resident interconnect structure
Assignee: Intersil Corp
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Filing: 1990-01-19
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Granted: 1991-12-03
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Expires: 2010-01-19
Abstract
Abstract Interconnect metal is selectively provided in a network of trenches formed in the top surface of a semiconductor substrate containing multiple circuit devices, electrical contact to regions of which is to be provided. The trench network is formed so that it intersects the device regions, thus exposing the regions at sidewalls of the trench. On the floor of the trench a bottom layer of insulator material is provided, and conductive material (such as tungsten) is deposited on or grown from the trench sidewalls, in order to electrically couple device regions to one another. Because the device interconnect employs a trench network, not only are top surface contact apertures unnecessary, but, with a device region contact (from the trench sidewall) being made along the entire width of the region, device resistance can be decreased and performance improved.
Inventors
- 👤 William R. Wade
- 👤 Kenneth A. Ports
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 22:03
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/20; Y; Y10; Y10S; Y10S257/00; Y10S257/911
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
102 words
An integrated circuit architecture for supporting a plurality of field effect devices therein comprising: a semiconductor substrate having a plurality of field effect devices in spaced apart surface portions thereof, each field effect device including source and drain regions and a gate therebetween; a trench formed in said substrate so that said trench intersects source and drain regions of said field effect devices and thereby exposes source and drain regions at sidewalls of said trench; and conductive material disposed in said trench in contact with the entirety of the width of source and drain regions exposed at the sidewalls of said trench.
Claim 2
Dependent Claim
102 words
An integrated circuit architecture for supporting a plurality of field effect devices therein comprising: a semiconductor substrate having a plurality of field effect devices in spaced apart surface portions thereof, each field effect device including source and drain regions and a gate therebetween; a trench formed in said substrate so that said trench intersects source and drain regions of said field effect devices and thereby exposes source and drain regions at sidewalls of said trench; and conductive material disposed in said trench in contact with the entirety of the width of source and drain regions exposed at the sidewalls of said trench.
Claim 3
Dependent Claim
24 words
An integrated circuit architecture according to claim 1, further including an insulator layer disposed on the bottom of said trench beneath said conductive material.
Claim 4
Dependent Claim
132 words
In a semiconductor on insulator integrated circuit architecture, including a semiconductor substrate having a buried insulator layer separating said substrate into an upper body portion and a lower body portion, said upper body portion containing a plurality of field effect devices, each of which has source and drain regions and a gate therebetween, and conductive material for providing electrical contact with source and drain regions of said devices, the improvement comprising a trench formed in the upper body portion of said substrate so that said trench intersects source and drain regions of said field effect devices and thereby exposes source and drain regions at sidewalls of said trench, and wherein said conductive material is disposed in said trench in contact with source and drain regions exposed at the sidewalls of said trench.
Claim 5
Dependent Claim
132 words
In a semiconductor on insulator integrated circuit architecture, including a semiconductor substrate having a buried insulator layer separating said substrate into an upper body portion and a lower body portion, said upper body portion containing a plurality of field effect devices, each of which has source and drain regions and a gate therebetween, and conductive material for providing electrical contact with source and drain regions of said devices, the improvement comprising a trench formed in the upper body portion of said substrate so that said trench intersects source and drain regions of said field effect devices and thereby exposes source and drain regions at sidewalls of said trench, and wherein said conductive material is disposed in said trench in contact with source and drain regions exposed at the sidewalls of said trench.
Claim 6
Dependent Claim
24 words
The improvement according to claim 3, wherein said trench includes an insulator layer disposed on the bottom of said trench beneath said conductive material.
Claim 7
Dependent Claim
34 words
The improvement according to claim 1, wherein each of said field effect semiconductor devices includes lateral isolation material extending from spaced apart surface portions of said upper body portion to said buried insulator layer.
Claim 8
Dependent Claim
91 words
An integrated circuit structure comprising: a semiconductor substrate having a plurality of circuit devices formed in respective spaced apart surface portions thereof, each of said circuit devices including at least one semiconductor region therein; a trench formed in said substrate so that said trench intersects semiconductor regions of plural ones of said circuit devices and thereby exposes said semiconductor regions at sidewalls of said trench; and conductive material formed in said trench in contact with sidewalls thereof so as to electrically interconnect semiconductor regions of plural ones of said circuit devices.
Claim 9
Dependent Claim
91 words
An integrated circuit structure comprising: a semiconductor substrate having a plurality of circuit devices formed in respective spaced apart surface portions thereof, each of said circuit devices including at least one semiconductor region therein; a trench formed in said substrate so that said trench intersects semiconductor regions of plural ones of said circuit devices and thereby exposes said semiconductor regions at sidewalls of said trench; and conductive material formed in said trench in contact with sidewalls thereof so as to electrically interconnect semiconductor regions of plural ones of said circuit devices.
Claim 10
Dependent Claim
25 words
An semiconductor integrated circuit structure according to claim 6, further including an insulator layer disposed on the bottom of said trench beneath said conductive material.
Claim 11
Dependent Claim
60 words
An integrated circuit structure according to claim 7, wherein said insulator layer is formed in said trench such that an interface between a semiconductor region and adjacent semiconductor material intersects said insulator layer in said trench, and said conductive material is formed on said insulator layer in said trench so as to electrically interconnect semiconductor regions of plural circuit devices.
Claim 12
Dependent Claim
17 words
An integrated circuit structure according to claim 8, wherein said conductive material includes regions of differing resistivity.
Claim 13
Dependent Claim
48 words
An integrated circuit structure according to claim 6, wherein said insulator layer has an aperture therethrough exposing material at the bottom of said trench, and said conductive material electrically couples a semiconductor region of a circuit device to the material exposed through the aperture in said insulator layer.
Claim 14
Dependent Claim
89 words
An integrated circuit architecture for supporting a plurality of bipolar transistors therein comprising: a semiconductor substrate having a plurality of bipolar transistors in spaced apart surface portions thereof, each bipolar transistor including collector, base and emitter regions; a trench formed in said substrate so that said trench intersects regions of plural ones of said bipolar transistors and thereby exposes plural regions at sidewalls of said trench; and conductive material disposed in said trench in contact with prescribed ones of said plural regions exposed at the sidewalls of said trench.
Claim 15
Dependent Claim
89 words
An integrated circuit architecture for supporting a plurality of bipolar transistors therein comprising: a semiconductor substrate having a plurality of bipolar transistors in spaced apart surface portions thereof, each bipolar transistor including collector, base and emitter regions; a trench formed in said substrate so that said trench intersects regions of plural ones of said bipolar transistors and thereby exposes plural regions at sidewalls of said trench; and conductive material disposed in said trench in contact with prescribed ones of said plural regions exposed at the sidewalls of said trench.
Claim 16
Dependent Claim
24 words
An integrated circuit architecture according to claim 11, further including an insulator layer disposed on the bottom of said trench beneath said conductive material.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-12-02 | 1995-06-03 | 1995-12-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-12-02 | 1999-06-03 | 1999-12-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-12-02 | 2003-06-03 | 2003-12-03 | $7700.00 | Window Closed / Lapsed |