Patent CH308651A successfully refreshed from Google Patents.
US5072142A
Expired / Lapsed
US
⏱️ 0.0 years remaining
High frequency fet switch and driver circuit
Assignee: Mitsubishi Electric Corp
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Filing: 1990-08-02
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Granted: 1991-12-10
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Expires: 2010-08-02
Abstract
Abstract A semiconductor integrated circuit includes a first FET for controlling transfer of a high frequency signal, first and second capacitors connected to a gate of the first FET directly or through a resistor or a 1/4 wavelength line, a second FET having its drain connected to the first capacitor and its source grounded at high frequencies band, and a third FET having its drain connected to said second capacitor and its source grounded at high frequencies.
Inventors
- 👤 Noriyuki Tanino
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 21:22
CPC Classifications
H; H01; H01P; H01P1/00; H01P1/10; H01P1/15
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
153 words
A semiconductor integrated circuit comprising: a first FET having a gate, a source, and a drain for controlling transfer of a high frequency signal; first and second capacitors, each having first and second terminals, the first terminals of the first and second capacitors being connected to the gate of said first FET; a second FET having a gate, a source, and a drain, the drain of said second FET being connected to the second terminal of said first capacitor, the source of said second FET being grounded at high frequencies, and the gate of the second FET receiving a first drive signal; and a third FET having a gate, a source, and a drain, the drain of said third FET being connected to the second terminal of said second capacitor, the source of said third FET being grounded at high frequencies, and the gate of the third FET receiving a second drive signal.
Claim 2
Dependent Claim
153 words
A semiconductor integrated circuit comprising: a first FET having a gate, a source, and a drain for controlling transfer of a high frequency signal; first and second capacitors, each having first and second terminals, the first terminals of the first and second capacitors being connected to the gate of said first FET; a second FET having a gate, a source, and a drain, the drain of said second FET being connected to the second terminal of said first capacitor, the source of said second FET being grounded at high frequencies, and the gate of the second FET receiving a first drive signal; and a third FET having a gate, a source, and a drain, the drain of said third FET being connected to the second terminal of said second capacitor, the source of said third FET being grounded at high frequencies, and the gate of the third FET receiving a second drive signal.
Claim 3
Dependent Claim
72 words
A semiconductor integrated circuit in accordance with claim 1 comprising: a first resistor connected in parallel with said first capacitor; a second resistor connected in parallel with said second capacitor; and a third resistor having first and second terminals, the first terminal of said third resistor being connected to the first terminals of said first and second capacitors and the second terminal of said third resistor being connected to a fixed potential.
Claim 4
Dependent Claim
26 words
A semiconductor integrated circuit in accordance with claim 1 wherein said first FET comprises one of a normally ON type FET and normally OFF type FET.
Claim 5
Dependent Claim
59 words
A semiconductor integrated circuit in accordance with claim 1 including input and output terminals and input and output microwave transmission lines wherein the source of said first FET is connected to the output terminal through said first microwave transmission line and the drain of said first FET is connected to the input terminal through said second microwave transmission line.
Claim 6
Dependent Claim
38 words
A semiconductor integrated circuit in accordance with claim 4 comprising first and second DC blocking capacitors respectively connected between said first microwave transmission line and the output terminal and said second microwave transmission line and the input terminal.
Claim 7
Dependent Claim
23 words
A semiconductor integrated circuit in accordance with claim 4 including a source bias circuit connected to the source terminal of said first FET.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-12-09 | 1995-06-10 | 1995-12-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-12-09 | 1999-06-10 | 1999-12-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-12-09 | 2003-06-10 | 2003-12-10 | $7700.00 | Window Closed / Lapsed |