US5072407A
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Serial data rate detection method and apparatus
Assignee: Microsemi Semiconductor ULC
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Filing: 1990-01-08
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Granted: 1991-12-10
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Expires: 2010-01-08
Abstract
Abstract A system and method are described for bit rate detection in a serial data communication system, the system employing a data rate prompt of a pair of opposite value data bits which follow a series of idle bits. In a first embodiment a receiving port employs a clocked delay element and a set of data clock rates, each data clock rate being a multiple N of one of a set of established bit transmission rates, ranging from a highest expected bit rate to a lowest expected bit rate. The bit rate detection method comprises: clocking the delay element at the highest data clock rate, upon the sensing of one of the opposite value data rate prompt bits at the delay element, to step the value of the sensed bit into the delay element. After a predetermined number of data clock pulses have stepped the value of the sensed bit into the delay element, the system compares the bit value at an input to the delay element and the bit value in a bit position of the delay element. If the comparison indicates an equality of bit values, the delay element is clocked at a lower data clock rate until the comparing step indicates an inequality of bit values. At this point, the bit rate has been determined. Another embodiment is also described wherein a pair of counters are substituted for the delay element.
Inventors
- 👤 Steven J. Gutz
- 👤 Charles M. Storry
- 👤 Craig P. Twardy
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 22:32
CPC Classifications
H; H04; H04L; H04L25/00; H04L25/02; H04L25/0262
Claims Analysis
Total Claims: 24
Claim 1
Independent Claim
188 words
A method for bit rate detection in a serial data communications system, said system employing a rate prompt of a pair of opposite value data bits which follow a series of idle data bits, and further comploying a clocked delay element and generator means for providing a set of data clock rates, each rate being a multiple N of one of a set of established bit transmission rates, ranging from a highest expected bit rate to a lowest expected bit rate, the method comprising: a. clocking said delay element at the highest data clock rate, upon the sensing of one of said opposite value bits at said delay element, to step the value of said sensed bit into said delay element; b. comparing, after a number of data clock pulses have stepped the value of said sensed bit into said delay element, a received bit value and the value of said sensed bit in a bit position of said delay element; and c. clocking said delay element at a lower data clock rate from said generator means if said comparing step (b) indicates an equality of bit values.
Claim 2
Independent Claim
188 words
A method for bit rate detection in a serial data communications system, said system employing a rate prompt of a pair of opposite value data bits which follow a series of idle data bits, and further comploying a clocked delay element and generator means for providing a set of data clock rates, each rate being a multiple N of one of a set of established bit transmission rates, ranging from a highest expected bit rate to a lowest expected bit rate, the method comprising: a. clocking said delay element at the highest data clock rate, upon the sensing of one of said opposite value bits at said delay element, to step the value of said sensed bit into said delay element; b. comparing, after a number of data clock pulses have stepped the value of said sensed bit into said delay element, a received bit value and the value of said sensed bit in a bit position of said delay element; and c. clocking said delay element at a lower data clock rate from said generator means if said comparing step (b) indicates an equality of bit values.
Claim 3
Dependent Claim
36 words
The method of claim 1 further comprising the additional steps of: d. employing said data clock rate to determine the value of received data bits when said comparing step (b) indicates an inequality of bit values.
Claim 4
Dependent Claim
53 words
The method of claim 2 wherein each data bit has a predetermined time duration which depends upon the expected bit transmission rate, said delay element, when clocked at said highest data clock rate, having a delay time which exceeds said predetermined time duration of a data bit at said highest bit transmission rate.
Claim 5
Dependent Claim
45 words
The method of claim 3 wherein said delay element has about 1.5N storage positions and said comparing step detects the bit value stored in the last of said 1.5N storage positions and compares it with the bit value at an input to said delay element.
Claim 6
Dependent Claim
32 words
The method of claim 4 further comprising the step of: e. prior to step (a), initializing all storage positions in said delay element by forcing each to store the same bit value.
Claim 7
Dependent Claim
33 words
The method of claim 5, further comprising the step of: f. delaying step (c) until a plurality of storage positions in said delay element have been forced to store the same bit value.
Claim 8
Dependent Claim
20 words
The method of claim 6 wherein step (f) forces ones into the last N/2 storage positions of said delay element.
Claim 9
Dependent Claim
17 words
The method of claim 7 wherein step (e) forces all ones into said delay element storage positions.
Claim 10
Dependent Claim
32 words
The method of claim 8 wherein said rate prompt comprises a zero level bit followed by a one level bit and said step (a) commences when said zero level bit is sensed.
Claim 11
Dependent Claim
18 words
The method of claim 9 wherein said idle data bits comprise a run of one level bit values.
Claim 12
Dependent Claim
249 words
Apparatus for bit rate detection in a serial data communication system, said system employing a rate prompt of a pair of opposite value data bits which follow a series of idle data bits, the apparatus comprising: multistage delay element having an input for receiving data signals and a stepping input for causing a signal at said input to be stepped through said multistages to a selected stage; means for generating a plurality of data clock rates, each rate being a multiple N of one of a set of established bit transmission rates, such transmission rates ranging from a highest rate to a lowest rate; comparison means connected to said selected stage of said multistage delay element and said delay element input, for providing an output indicative of the identity or difference of data levels at said selected stage and said input; and processor control means connected to said multistage delay element, said data clock rate generating means and said comparison means for enabling said generating means to apply said highest data clock rate to said stepping input upon sensing one of said opposite value data bits at said input, to thereby step the value of said sensed data bit into said delay element and to said selected stage, and for responding to an identity output from said comparison means, indicating a said data bit prompt has not been fully stepped into said delay element, to cause said data clock rate generating means to produce a lower data clock rate.
Claim 13
Dependent Claim
249 words
Apparatus for bit rate detection in a serial data communication system, said system employing a rate prompt of a pair of opposite value data bits which follow a series of idle data bits, the apparatus comprising: multistage delay element having an input for receiving data signals and a stepping input for causing a signal at said input to be stepped through said multistages to a selected stage; means for generating a plurality of data clock rates, each rate being a multiple N of one of a set of established bit transmission rates, such transmission rates ranging from a highest rate to a lowest rate; comparison means connected to said selected stage of said multistage delay element and said delay element input, for providing an output indicative of the identity or difference of data levels at said selected stage and said input; and processor control means connected to said multistage delay element, said data clock rate generating means and said comparison means for enabling said generating means to apply said highest data clock rate to said stepping input upon sensing one of said opposite value data bits at said input, to thereby step the value of said sensed data bit into said delay element and to said selected stage, and for responding to an identity output from said comparison means, indicating a said data bit prompt has not been fully stepped into said delay element, to cause said data clock rate generating means to produce a lower data clock rate.
Claim 14
Dependent Claim
47 words
The apparatus as defined in claim 11 wherein said processor control means responds to a difference output from said comparison means by continuing said highest data clock rate and by determining that an alphanumeric, of which said rate prompt is a part, is a proper prompt alphanumeric.
Claim 15
Dependent Claim
16 words
The apparatus as defined in claim 12 wherein said comparison means is an exclusive OR circuit.
Claim 16
Dependent Claim
31 words
The apparatus as defined in claim 12 wherein said multistage delay element is provided with about 1.5 N stages and said selected stage is a last stage in said delay element.
Claim 17
Dependent Claim
70 words
The apparatus as defined in claim 14 further comprising means connected to said processor control means and responsive to an identity output from said comparison means, to set to a predetermined logic state a plurality of latter stages of said multistage delay element, said processor control means only responding to an output from said comparison means when said input data bit value has again been stepped to said selected stage.
Claim 18
Independent Claim
185 words
A method for bit rate detection in a serial communications system, said system employing a rate prompt of a pair of opposite value data bits which follow a series of idle data bits, and further employing a clockable element and generating means for providing a set of data clock rates, each rate being a multiple N of one of a set of established bit transmission rates, ranging from a highest expected bit rate to a lowest expected bit rate, the method comprising: a. clocking said element at the highest data clock rate of said set, upon the sensing of one of said opposite value bits at said clockable element, to cause said element to accumulate said clock pulses; b. determining, after a number of clock pulses have been accumulated in said element, whether the bit value at an input to said element is at a different bit value from the bit value when said clocking in step (a) commenced; and c. clocking said element at a lower data clock rate from said generating means if said determining step (b) indicates an equality of bit values.
Claim 19
Independent Claim
185 words
A method for bit rate detection in a serial communications system, said system employing a rate prompt of a pair of opposite value data bits which follow a series of idle data bits, and further employing a clockable element and generating means for providing a set of data clock rates, each rate being a multiple N of one of a set of established bit transmission rates, ranging from a highest expected bit rate to a lowest expected bit rate, the method comprising: a. clocking said element at the highest data clock rate of said set, upon the sensing of one of said opposite value bits at said clockable element, to cause said element to accumulate said clock pulses; b. determining, after a number of clock pulses have been accumulated in said element, whether the bit value at an input to said element is at a different bit value from the bit value when said clocking in step (a) commenced; and c. clocking said element at a lower data clock rate from said generating means if said determining step (b) indicates an equality of bit values.
Claim 20
Dependent Claim
36 words
The method of claim 16 further comprising the additional step of: d. employing the data clock rate to determine the value of received data bits when said determining step (b) indicates a difference of bit values.
Claim 21
Dependent Claim
13 words
The method of claim 17 wherein said clockable element is a first counter.
Claim 22
Dependent Claim
106 words
The method claim 18 wherein said system includes a second counter and a data latch, said method comprising after step d, the further steps of: e. setting said data latch to manifest the level of said bit value at said first counter in step (a), said setting occurring a predetermined number of counts after commencement of said counting; and f. resetting said data latch to an opposite bit value when said second counter reaches a predetermined count, said count being commenced in response to a predetermined count of said first counter and the occurrence of an opposite level bit value from said serial data communications system.
Claim 23
Independent Claim
238 words
A method for bit rate detection in a serial data communications system, said system employing a rate prompt of a pair of opposite value data bits which follow a series of idle data bits, and further employing a clocked delay element, a counter and a set of data clock rates, each rate being a multiple N of one of a set of established bit transmission rates, ranging from a highest expected bit rate to a lowest expected bit rate, the method comprising: a. clocking said delay element at the highest data clock rate, upon the sensing of one of said opposite value bits at said delay element, to step the value of said sensed bit into said delay element; b. operating said counter at said highest data clock rate upon a start of said clocking in step (a); c. determining, after a number of data clock pulses have caused said counter to manifest a count, whether the bit value at an input to said delay element is different from the bit value when said clocking step (a) commenced; d. clocking said delay element at a lower data clock rate if said comparing step (b) indicates an equality of bit values and continuing to operate said counter at said highest data clock rate; and e. employing the data clock rate to determine the value of received data bits when said determining step (c) indicates a difference of bit values.
Claim 24
Independent Claim
238 words
A method for bit rate detection in a serial data communications system, said system employing a rate prompt of a pair of opposite value data bits which follow a series of idle data bits, and further employing a clocked delay element, a counter and a set of data clock rates, each rate being a multiple N of one of a set of established bit transmission rates, ranging from a highest expected bit rate to a lowest expected bit rate, the method comprising: a. clocking said delay element at the highest data clock rate, upon the sensing of one of said opposite value bits at said delay element, to step the value of said sensed bit into said delay element; b. operating said counter at said highest data clock rate upon a start of said clocking in step (a); c. determining, after a number of data clock pulses have caused said counter to manifest a count, whether the bit value at an input to said delay element is different from the bit value when said clocking step (a) commenced; d. clocking said delay element at a lower data clock rate if said comparing step (b) indicates an equality of bit values and continuing to operate said counter at said highest data clock rate; and e. employing the data clock rate to determine the value of received data bits when said determining step (c) indicates a difference of bit values.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-12-09 | 1995-06-10 | 1995-12-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-12-09 | 1999-06-10 | 1999-12-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-12-09 | 2003-06-10 | 2003-12-10 | $7700.00 | Window Closed / Lapsed |