Patent US4084236A successfully refreshed from Google Patents.
US5084418A
Expired / Lapsed
US
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Method of making an array device with buried interconnects
Assignee: Texas Instruments Inc
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Filing: 1990-01-16
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Granted: 1992-01-28
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Expires: 2010-01-16
Abstract
Abstract Bitlines (34) are formed by creating a diffused region (26) around the sidewalls and bottom of a trench (20). The trench (20) is filled with a conductive region (30), typically a refractory metal, refractory metal silicide.
Inventors
- 👤 Agerico L. Esquivel
- 👤 Howard L. Tigelaar
- 👤 Allan T. Mitchell
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 18:44
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/20; H10W20/01; H10W20/021
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
91 words
A method for forming an array containing at least two devices on a substrate, comprising the steps of: forming at least one conductive lead extending between said devices, said lead formed by a process comprising the steps of: forming a trench in the surface of said substrate extending between said devices; doping the surfaces of said trench to provide a doped layer surrounding said trench of opposite conductivity type of said substrate; and filling said trench with a conductive material, said conductive material being in conductive contact with said doped layer.
Claim 2
Independent Claim
91 words
A method for forming an array containing at least two devices on a substrate, comprising the steps of: forming at least one conductive lead extending between said devices, said lead formed by a process comprising the steps of: forming a trench in the surface of said substrate extending between said devices; doping the surfaces of said trench to provide a doped layer surrounding said trench of opposite conductivity type of said substrate; and filling said trench with a conductive material, said conductive material being in conductive contact with said doped layer.
Claim 3
Dependent Claim
22 words
A method as in claim 1 wherein said trench extends from one side of said array to another side of said array.
Claim 4
Dependent Claim
12 words
A method as in claim 1 wherein said substrate comprises crystalline silicon.
Claim 5
Dependent Claim
17 words
A method as in claim 1 wherein said lead is a bit line in a memory array.
Claim 6
Dependent Claim
39 words
A method as in claim 1 wherein said doping of the surfaces of said trench includes the steps of forming a first doped region on the surface of said substrate and forming said trench through said first doped region.
Claim 7
Dependent Claim
49 words
A method as in claim 5 wherein said doping of the surfaces of said trench includes the steps of forming a second doped region in the bottom of said trench and causing said first and second doped regions to diffuse into said substrate to form a contiguous doped region.
Claim 8
Dependent Claim
47 words
A method as in claim 1 wherein said doping of the surfaces of said trench includes the steps of depositing a dopant carrying layer on the surfaces of said trench and causing the dopant in said dopant carrying layer to diffuse into the surfaces of said trench.
Claim 9
Dependent Claim
14 words
A method as in claim 1 wherein said conductive material is a metal silicide.
Claim 10
Dependent Claim
21 words
A method as in claim 8 wherein said metal silicide is selected from the group of titanium silicide and tungsten silicide.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-01-27 | 1995-07-29 | 1996-01-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-01-27 | 1999-07-29 | 2000-01-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-01-27 | 2003-07-29 | 2004-01-28 | $7700.00 | Window Closed / Lapsed |