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US5084635A
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Function selector circuit
Assignee: Toshiba Corp
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Filing: 1990-09-27
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Granted: 1992-01-28
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Expires: 2010-09-27
Abstract
Abstract A function selection circuit includes a first signal generating circuit for generating a plurality of first signals corresponding to each of all combinations of a plurality of input signal states; and a second signal generating circuit for selecting a plurality of logical sums of combinations of the plurality of first signals and generating a second signal corresponding to each of the plurality of logical sums which selectively activates an operation function indicated by a truth table.
Inventors
- 👤 Haruki Toda
- 👤 Shigeo Ohshima
- 👤 Tatsuo Ikawa
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 20:23
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C7/00; G11C7/10; G11C7/1075; G11C7/1015
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
126 words
A function selection circuit comprising: first signal generating means for generating a plurality of first signals each corresponding to each of all combinations of a plurality of input signal states; and second signal generating means for selecting a plurality of logical sums of combinations of said plurality of first signals and generating a second signal corresponding to each of said plurality of logical sums which selectively activates an operation function indicated by a truth table, said truth table indicating the relationship between the combinations of said plurality of input signal states and various operation functions; whereby an operation function indicated by said truth table and corresponding to each of the combinations of said plurality of input signal states is selected, in accordance with said truth table.
Claim 2
Dependent Claim
126 words
A function selection circuit comprising: first signal generating means for generating a plurality of first signals each corresponding to each of all combinations of a plurality of input signal states; and second signal generating means for selecting a plurality of logical sums of combinations of said plurality of first signals and generating a second signal corresponding to each of said plurality of logical sums which selectively activates an operation function indicated by a truth table, said truth table indicating the relationship between the combinations of said plurality of input signal states and various operation functions; whereby an operation function indicated by said truth table and corresponding to each of the combinations of said plurality of input signal states is selected, in accordance with said truth table.
Claim 3
Dependent Claim
38 words
A function selector circuit according to claim 1, wherein said first signal generating means latches a signal state of input signals at a predetermined timing, and generates said first signal corresponding to the combination of latched signal states.
Claim 4
Dependent Claim
38 words
A function selector circuit according to claim 1, wherein said second signal generator outputs a logical sum of the state of said first signals during a predetermined period, and becomes disabled during periods other than said predetermined period.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-01-27 | 1995-07-29 | 1996-01-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-01-27 | 1999-07-29 | 2000-01-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-01-27 | 2003-07-29 | 2004-01-28 | $7700.00 | Window Closed / Lapsed |