US5087955A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Input-output circuit of reduced device area for semicustom semiconductor integrated circuit
Assignee: NEC Electronics Corp
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Filing: 1990-08-08
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Granted: 1992-02-11
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Expires: 2010-08-08
Abstract
Abstract A peripheral block of a semicustom integrated circuit comprises one input/output pad formed on a peripheral portion of a substrate and an N-channel MOS transistor formed in proximity of the input/output pad. A wiring conductor extends from the input/output pad to an internal circuit, and one the way, is connected to a drain region of the N-channel MOS transistor. A source and a gate of the N-channel MOS transistor is connected to a ground so as to function as a diode for protecting a large voltage inputted to the input/output pad, from the internal circuit.
Inventors
- 👤 Haruji Futami
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 03:35
CPC Classifications
H; H10; H10D; H10D89/00; H10D89/60; H10D89/601; H10D89/611; H10D84/00; H10D84/90; H10D84/998
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
197 words
A peripheral block of a semicustom integrated circuit comprising: one input/output pad formed on a peripheral portion of a substrate, an N-channel MOS transistor formed in proximity of said input/output pad and having a drain region connected to said input/output pad and an internal circuit, a source and a gate of said N-channel MOS transistor being connected to a ground; a first level conductor connected to said input/output pad and extending toward said internal circuit through a region in which said N-channel MOS transistor is formed, said conductor being connected to said drain region of said N-channel MOS transistor above said drain region of said N-channel MOS transistor by means of contacts; and a second level conductor is positioned above said first level conductor and to cover said N-channel MOS transistor, said second level conductor being connected to said source region of said N-channel MOS transistor by means of through-holes and connected to the ground level; wherein said gate of said N-channel MOS transistor is connected through a contact to said substrate and said substrate itself is grounded so that said gate of said N-channel MOS transistor is grounded through a resistive component of said substrate itself.
Claim 2
Dependent Claim
197 words
A peripheral block of a semicustom integrated circuit comprising: one input/output pad formed on a peripheral portion of a substrate, an N-channel MOS transistor formed in proximity of said input/output pad and having a drain region connected to said input/output pad and an internal circuit, a source and a gate of said N-channel MOS transistor being connected to a ground; a first level conductor connected to said input/output pad and extending toward said internal circuit through a region in which said N-channel MOS transistor is formed, said conductor being connected to said drain region of said N-channel MOS transistor above said drain region of said N-channel MOS transistor by means of contacts; and a second level conductor is positioned above said first level conductor and to cover said N-channel MOS transistor, said second level conductor being connected to said source region of said N-channel MOS transistor by means of through-holes and connected to the ground level; wherein said gate of said N-channel MOS transistor is connected through a contact to said substrate and said substrate itself is grounded so that said gate of said N-channel MOS transistor is grounded through a resistive component of said substrate itself.
Claim 3
Dependent Claim
136 words
A peripheral block of a semicustom integrated circuit comprising one input/output pad formed on a peripheral portion of a substrate, a wiring conductor extending from said input/output pad towards an internal circuit, an N-channel MOS transistor formed in proximity of said input/output pad and in the path of said wiring conductor, a drain region of said N-channel MOS transistor being connected to said wiring conductor, a source and a gate of said N-channel MOS transistor being connected to a ground, and an P-channel MOS transistor formed in an N-well formed in proximity of said N-channel MOS transistor and in the path of said wiring conductor, a drain region of said P-channel MOS transistor being connected to said wiring conductor, a source and a gate of said P-channel MOS transistor being connected to a high voltage line.
Claim 4
Dependent Claim
136 words
A peripheral block of a semicustom integrated circuit comprising one input/output pad formed on a peripheral portion of a substrate, a wiring conductor extending from said input/output pad towards an internal circuit, an N-channel MOS transistor formed in proximity of said input/output pad and in the path of said wiring conductor, a drain region of said N-channel MOS transistor being connected to said wiring conductor, a source and a gate of said N-channel MOS transistor being connected to a ground, and an P-channel MOS transistor formed in an N-well formed in proximity of said N-channel MOS transistor and in the path of said wiring conductor, a drain region of said P-channel MOS transistor being connected to said wiring conductor, a source and a gate of said P-channel MOS transistor being connected to a high voltage line.
Claim 5
Dependent Claim
47 words
A peripheral block of a semicustom integrated circuit as claimed in claim 2 wherein said gate of said N-channel MOS transistor is connected to the ground through a resistor and said gate of said P-channel MOS transistor being connected to the high voltage line through a resistor.
Claim 6
Dependent Claim
108 words
A peripheral block of a semicustom integrated circuit as claimed in claim 3 wherein said wiring conductor is composed of a first level conductor connected to said input/output pad and extending toward said internal circuit through a region in which said N-channel MOS transistor is formed and through another region in which said P-channel transistor is formed, said first level conductor being connected to said drain region of said N-channel MOS transistor above said drain region of said N-channel MOS transistor by means of contacts and to said drain region of said P-channel MOS transistor above said drain region of said P-channel MOS transistor by means of contacts.
Claim 7
Dependent Claim
112 words
A peripheral block of a semicustom integrated circuit as claimed in claim 4 further including a ground conductor positioned at a second level higher than said first level conductor and to cover said N-channel MOS transistor, said ground conductor being connected to said source region of said N-channel MOS transistor by means of through-holes and also connected to the ground level, and a high voltage conductor is positioned at a second level higher than said first level conductor and to cover said P-channel MOS transistor, said high voltage conductor being connected to said source region of said P-channel MOS transistor by means of through-holes and also connected to said high voltage line.
Claim 8
Dependent Claim
106 words
A peripheral block of a semicustom integrated circuit as claimed in claim 5 wherein said gate of said N-channel MOS transistor is connected through a contact to said substrate and said substrate itself is grounded so that said gate of said N-channel MOS transistor is grounded through a resistive component of said substrate itself, and wherein said gate of said P-channel MOS transistor is connected through a contact to said N-well and said N-well is connected to said high voltage conductor so that the said gate of said P-channel MOS transistor is connected to said high voltage conductor through a resistive component of said N-well itself.
Claim 9
Dependent Claim
188 words
An integrated circuit including a plurality of unitary circuits formed on a semiconductor substrate, each of said unitary circuits including an electrode pad to be connected to an external circuit and at least one MOS transistor, wherein a first unitary circuit of said unitary circuits includes a first wiring for connecting said electrode pad of said first unitary circuit to an internal circuit, a second wiring for connecting a source-drain path of said MOS transistor of said first unitary circuit between said first wiring and a voltage supply wiring, and a third wiring for connecting a gate of said MOS transistor to said voltage supply wiring, so that said first unitary circuit constitutes an input circuit for the integrated circuit, and wherein a second unitary circuit of said unitary circuits includes a fourth wiring for connecting a gate of said MOS transistor of said second unitary circuit to an internal circuit, and a fifth wiring for connecting a source-drain path between said electrode pad of said second unitary circuit and said voltage supply wiring, so that said second unitary circuit constitutes an output circuit for the integrated circuit.
Claim 10
Dependent Claim
188 words
An integrated circuit including a plurality of unitary circuits formed on a semiconductor substrate, each of said unitary circuits including an electrode pad to be connected to an external circuit and at least one MOS transistor, wherein a first unitary circuit of said unitary circuits includes a first wiring for connecting said electrode pad of said first unitary circuit to an internal circuit, a second wiring for connecting a source-drain path of said MOS transistor of said first unitary circuit between said first wiring and a voltage supply wiring, and a third wiring for connecting a gate of said MOS transistor to said voltage supply wiring, so that said first unitary circuit constitutes an input circuit for the integrated circuit, and wherein a second unitary circuit of said unitary circuits includes a fourth wiring for connecting a gate of said MOS transistor of said second unitary circuit to an internal circuit, and a fifth wiring for connecting a source-drain path between said electrode pad of said second unitary circuit and said voltage supply wiring, so that said second unitary circuit constitutes an output circuit for the integrated circuit.
Claim 11
Dependent Claim
99 words
An integrated circuit including first and second electrode pads, a first wiring for connecting said first electrode pad to an internal circuit, a first MOS transistor having a source-drain path connected between said first wiring and a voltage supply line and a gate electrically connected to said voltage supply line, a second MOS transistor having a source-drain path connected between said second electrode pad and said voltage supply line and having substantially the same size as that of said first MOS transistor, and a second wiring for connecting a gate of said second MOS transistor to an internal circuit.
Claim 12
Dependent Claim
99 words
An integrated circuit including first and second electrode pads, a first wiring for connecting said first electrode pad to an internal circuit, a first MOS transistor having a source-drain path connected between said first wiring and a voltage supply line and a gate electrically connected to said voltage supply line, a second MOS transistor having a source-drain path connected between said second electrode pad and said voltage supply line and having substantially the same size as that of said first MOS transistor, and a second wiring for connecting a gate of said second MOS transistor to an internal circuit.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-02-10 | 1995-08-12 | 1996-02-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-02-10 | 1999-08-12 | 2000-02-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-02-10 | 2003-08-12 | 2004-02-11 | $7700.00 | Window Closed / Lapsed |