US5088060A
Expired / Lapsed
US
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Electrically erasable programmable read-only memory with NAND memory cell structure
Assignee: Toshiba Corp
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Filing: 1990-12-26
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Granted: 1992-02-11
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Expires: 2010-12-26
Abstract
Abstract An electrically erasable programmable read-only memory with a NAND cell structure has parallel bit lines, and memory cells defining NAND cell blocks, each of which has a series-circuit of memory cell transistors. Each transistor has a floating gate and a control gate. Parallel word lines are connected to the control gates of the cell transistors. The first, second and third intermediate voltages are used in the data write mode: the first voltage is lower than the "H" level voltage and higher than the "L" level voltage; the second and third voltages are higher than the first voltage and lower than the "H" level voltage. Data is written into a selected memory cell transistor of a NAND cell block, by applying the "H" level voltage to a word line connected to the selected transistor, applying the second voltage to the remaining unselected word lines, applying a corresponding bit line associated with the selected transistor with one of the first and third voltages which is selected in accordance with a logic level of the data, and applying unselected bit lines with the third voltage, whereby carriers are moved by tunneling from or to the floating gate of the selected memory cell transistor.
Inventors
- 👤 Tetsuo Endoh
- 👤 Riichiro Shirota
- 👤 Masaki Momodomi
- 👤 Tomoharu Tanaka
- 👤 Fujio Masuoka
- 👤 Shigeyoshi Watanabe
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 04:51
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/04; G11C16/0483
Claims Analysis
Total Claims: 25
Claim 1
Independent Claim
220 words
A non-volatile semiconductor memory device comprising: a semiconductive substrate; bit lines on said substrate; word lines insulatively crossing said bit lines to define crossing points therebetween on said substrate; an array of memory cells at the crossing points on said substrate, each of said memory cells including one transistor with a carrier storage layer and a control gate; said array of memory cells including two adjacent, first and second memory cell transistors which are connected at their control gates in common to one of said word lines and which have heavily-doped semiconductive regions that define a source and a drain of a transistor structure for turning on, when one of these memory cell transistors is selected for data write, so that leak current flows therebetween; leak current eliminator means for forcing said transistor structure to turn off during data write for the selected memory cell transistor, by causing potential difference between said heavily-doped semiconductive regions to be low enough to render said transistor structure nonconductive even when a highest voltage is applied to said one of said word lines which serves as a gate electrode of said transistor structure; and said leak current eliminator means causing the potential difference to decrease by increasing a lower one of voltage potentials at said heavily-doped regions, while said transistor structure is rendered nonconductive.
Claim 2
Dependent Claim
220 words
A non-volatile semiconductor memory device comprising: a semiconductive substrate; bit lines on said substrate; word lines insulatively crossing said bit lines to define crossing points therebetween on said substrate; an array of memory cells at the crossing points on said substrate, each of said memory cells including one transistor with a carrier storage layer and a control gate; said array of memory cells including two adjacent, first and second memory cell transistors which are connected at their control gates in common to one of said word lines and which have heavily-doped semiconductive regions that define a source and a drain of a transistor structure for turning on, when one of these memory cell transistors is selected for data write, so that leak current flows therebetween; leak current eliminator means for forcing said transistor structure to turn off during data write for the selected memory cell transistor, by causing potential difference between said heavily-doped semiconductive regions to be low enough to render said transistor structure nonconductive even when a highest voltage is applied to said one of said word lines which serves as a gate electrode of said transistor structure; and said leak current eliminator means causing the potential difference to decrease by increasing a lower one of voltage potentials at said heavily-doped regions, while said transistor structure is rendered nonconductive.
Claim 3
Dependent Claim
41 words
The device according to claim 1, wherein said leak current eliminator means applies to one of said certain heavily-doped regions an intermediate voltage which has a potential intermediate between the highest voltage (Vh) and a lowest voltage (VL) of said device.
Claim 4
Dependent Claim
51 words
The device according to claim 2, wherein said array of memory cells are arranged in a plurality of memory cell units each of which has a series-circuit of a preselected number of memory cell transistors having carrier storage layers and control gates, said word lines being connected to said control gates.
Claim 5
Dependent Claim
36 words
The device according to claim 1, wherein said substrate comprises a semiconductor well region of a certain conductivity type opposite to that of said substrate, said array of memory cells being arranged in the well region.
Claim 6
Dependent Claim
31 words
The device according to claim 4, further comprising: means for applying to said well region a voltage of negative polarity while the selected memory cell transistor is subjected to data write.
Claim 7
Dependent Claim
18 words
The device according to claim 4, wherein said memory cell transistors comprise floating gate tunneling field effect transistors.
Claim 8
Dependent Claim
196 words
An electrically programmable non-volatile semiconductor memory comprising: a semiconductive substrate; parallel data transfer lines on said substrate; parallel program lines insulatively crossing said data transfer lines to define crossing points therebetween on said substrate; a plurality of memory cells at the crossing points on said substrate, said memory cells being arranged in a plurality of memory cell units each of which has a series-circuit of a preselected number of memory cell transistors having carrier storage layers, control gates, and heavily-doped regions in said substrate, said program lines being connected to said control gates; write controller means connected to said data transfer lines and program lines, for writing data into a selected memory cell transistor, by providing said program lines and said data transfer lines with specific voltages having a highest potential level and a plurality of intermediate potential levels which are defined between the highest potential level and a lowest potential level of said semiconductor memory; said write controller means preventing the heavily-doped regions of the selected cell transistor and a neighboring cell transistor thereof from having applied thereto the lowest potential level of said semiconductor memory while data is written into said selected cell transistor.
Claim 9
Dependent Claim
196 words
An electrically programmable non-volatile semiconductor memory comprising: a semiconductive substrate; parallel data transfer lines on said substrate; parallel program lines insulatively crossing said data transfer lines to define crossing points therebetween on said substrate; a plurality of memory cells at the crossing points on said substrate, said memory cells being arranged in a plurality of memory cell units each of which has a series-circuit of a preselected number of memory cell transistors having carrier storage layers, control gates, and heavily-doped regions in said substrate, said program lines being connected to said control gates; write controller means connected to said data transfer lines and program lines, for writing data into a selected memory cell transistor, by providing said program lines and said data transfer lines with specific voltages having a highest potential level and a plurality of intermediate potential levels which are defined between the highest potential level and a lowest potential level of said semiconductor memory; said write controller means preventing the heavily-doped regions of the selected cell transistor and a neighboring cell transistor thereof from having applied thereto the lowest potential level of said semiconductor memory while data is written into said selected cell transistor.
Claim 10
Dependent Claim
42 words
The memory according to claim 7, wherein said memory is adapted to be supplied with an external power supply voltage, said highest potential level is higher than the power supply voltage, said lowest potential level is lower than said power supply voltage.
Claim 11
Dependent Claim
34 words
The memory according to claim 8, wherein said intermediate potential levels include a first, a second, and a third d.c. potential level, at least one of which is lower than said power supply voltage.
Claim 12
Dependent Claim
45 words
The memory according to claim 8, wherein said intermediate potential levels includes a first, a second, and a third d.c. potential level, one of which is lower than said power supply voltage, and the remaining ones of which are higher than said power supply voltage.
Claim 13
Dependent Claim
34 words
The memory according to claim 8, wherein said plurality of memory cell units are arranged in a top surface portion of said substrate which is prevented from being provided with a semiconductive well region.
Claim 14
Dependent Claim
35 words
The memory according to claim 8, further comprising: a semiconductive well region of a certain conductivity type opposite to that of said substrate, said plurality of memory cell units being arranged in said well region.
Claim 15
Dependent Claim
18 words
The memory according to claim 8, wherein said plurality of memory cells comprise floating gate field effect transistors.
Claim 16
Dependent Claim
164 words
An electrically erasable and programmable read-only memory system comprising: an array of rows and columns of memory cells arranged in a plurality of memory cell units each of which has a plurality of memory cell transistors each having heavily-doped semiconductive regions in said substrate, a carrier storage layer and a control gate; bit lines associated with said memory cell units; word lines connected to the control gates of the rows of said memory cell transistors; and write controller means connected to said data transfer lines and program lines, for forcing carriers to move to or from the carrier storage layer of a selected memory cell transistor to write data thereinto, by providing said bit lines and said word lines with specific voltages including a high-level voltage and a plurality of intermediate voltages which are defined between the high-level voltage and a low-level voltage, one of said intermediate voltages having a potential lower than that of an external power supply voltage applied to said array.
Claim 17
Dependent Claim
164 words
An electrically erasable and programmable read-only memory system comprising: an array of rows and columns of memory cells arranged in a plurality of memory cell units each of which has a plurality of memory cell transistors each having heavily-doped semiconductive regions in said substrate, a carrier storage layer and a control gate; bit lines associated with said memory cell units; word lines connected to the control gates of the rows of said memory cell transistors; and write controller means connected to said data transfer lines and program lines, for forcing carriers to move to or from the carrier storage layer of a selected memory cell transistor to write data thereinto, by providing said bit lines and said word lines with specific voltages including a high-level voltage and a plurality of intermediate voltages which are defined between the high-level voltage and a low-level voltage, one of said intermediate voltages having a potential lower than that of an external power supply voltage applied to said array.
Claim 18
Dependent Claim
56 words
The system according to claim 14, wherein said write controller means prevents the heavily-doped regions of said memory cell transistors including the selected cell transistor and a neighboring cell transistor thereof, which are connected to one of said word lines, from having applied thereto the low-level voltage while data is written into said selected cell transistor.
Claim 19
Dependent Claim
36 words
The system according to claim 15, wherein said write controller means applies to said selected cell transistor and said neighboring cell transistor a voltage having a potential lower than that of the external power supply voltage.
Claim 20
Dependent Claim
44 words
The system according to claim 14, wherein said intermediate voltages have a first, a second, and a third d.c. potential level, one of which is lower than said power supply voltage, and the remaining ones of which are higher than said power supply voltage.
Claim 21
Dependent Claim
36 words
The system according to claim 14, further comprising a semiconductor substrate, said memory cell units being arranged in a top surface portion of said substrate which is prevented from being provided with a semiconductive well region.
Claim 22
Dependent Claim
37 words
The system according to claim 14, further comprising: a semiconductor substrate; and a semiconductive well region of a certain conductivity type opposite to that of said substrate, said memory cell units being arranged in said well region.
Claim 23
Dependent Claim
16 words
The system according to claim 14, wherein said memory cells comprise floating gate field effect transistors.
Claim 24
Dependent Claim
231 words
A non-volatile semiconductor memory device comprising: a semiconductive substrate having a top surface that is free from additional doping of impurity; parallel bit lines on said substrate; parallel word lines insulatively crossing said bit lines to define crossing points therebetween on said substrate; an array of memory cells at the crossing points on said top surface of said substrate, each of said memory cells including one transistor with a carrier storage layer and a control gate; said array of memory cells including two adjacent, first and second memory cell transistors which are connected at their control gates in common to one of said word lines and which have heavily-doped semiconductive regions that define a source and a drain of a transistor structure for turning on, when one of these memory cell transistors is selected for data write, so that leak current flows therebetween; leak current eliminator means for forcing said transistor structure to turn off during data write for the selected memory cell transistor, by causing potential difference between said heavily-doped semiconductive regions to be low enough to render said transistor structure nonconductive even when a highest voltage is applied to said one of said word lines which serves as a gate electrode of said transistor structure; and means for applying to said substrate a voltage of negative polarity while the selected memory cell transistor is subjected to a write operation.
Claim 25
Dependent Claim
231 words
A non-volatile semiconductor memory device comprising: a semiconductive substrate having a top surface that is free from additional doping of impurity; parallel bit lines on said substrate; parallel word lines insulatively crossing said bit lines to define crossing points therebetween on said substrate; an array of memory cells at the crossing points on said top surface of said substrate, each of said memory cells including one transistor with a carrier storage layer and a control gate; said array of memory cells including two adjacent, first and second memory cell transistors which are connected at their control gates in common to one of said word lines and which have heavily-doped semiconductive regions that define a source and a drain of a transistor structure for turning on, when one of these memory cell transistors is selected for data write, so that leak current flows therebetween; leak current eliminator means for forcing said transistor structure to turn off during data write for the selected memory cell transistor, by causing potential difference between said heavily-doped semiconductive regions to be low enough to render said transistor structure nonconductive even when a highest voltage is applied to said one of said word lines which serves as a gate electrode of said transistor structure; and means for applying to said substrate a voltage of negative polarity while the selected memory cell transistor is subjected to a write operation.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-02-10 | 1995-08-12 | 1996-02-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-02-10 | 1999-08-12 | 2000-02-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-02-10 | 2003-08-12 | 2004-02-11 | $7700.00 | Window Closed / Lapsed |