US5095454A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method and apparatus for verifying timing during simulation of digital circuits
Assignee: Gateway Design Automation Corp
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Filing: 1989-05-25
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Granted: 1992-03-10
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Expires: 2009-05-25
Abstract
Abstract A digital circuit simulation method and apparatus provide for critical path timing analysis of digital circuitry using a hybrid path tracing method. The hybrid path tracing performs path tracing when, for example, simulation values change at designated inputs. The path tracing can employ the simulation values for eliminating blocked paths. During tracing, the method and apparatus determine the shortest and longest paths from each input or beginning point to each end point. The end points are typically storage elements such as latches, flip-flops or systems outputs at a high functional level. The critical path tracing analysis finds the shortest and longest paths from the beginning point to the end point and records and saves the violation history, if any, associated with those paths. A timing template allows the user to develop the necessary input stimuli, in a logical ordered format to test the timing behavior of the digital circuit to be designed. Special procedures are also available for enabling the iteration of stimuli to check the timing of a transparent latch-based design. The system thus provides as an output either a summary or detailed history of violations at selected levels within the circuit to be analyzed. User input enables the system to isolate upon particular portions of the circuitry for determining correct operation.
Inventors
- 👤 Chi-Lai Huang
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 00:28
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/30; G01R31/3016; G06; G06F; G06F30/00; G06F30/30; G06F30/32; G06F30/33; G06F30/3308; G06F30/3312
Claims Analysis
Total Claims: 44
Claim 1
Independent Claim
96 words
A method for performing a timing analysis simulation upon a digital circuit design comprising the steps of inputting said digital circuit design to an analysis apparatus, simulating a logical function evaluation of said design for each of successive simulation time instants, performing a timing analysis of said digital circuit design using a path tracing analysis of said design from designated inputs to end points of signal propagation paths beginning at said designated inputs, and eliminating paths subject to said path tracing analysis depending upon the signal value results of said simulation step at said designated inputs.
Claim 2
Independent Claim
96 words
A method for performing a timing analysis simulation upon a digital circuit design comprising the steps of inputting said digital circuit design to an analysis apparatus, simulating a logical function evaluation of said design for each of successive simulation time instants, performing a timing analysis of said digital circuit design using a path tracing analysis of said design from designated inputs to end points of signal propagation paths beginning at said designated inputs, and eliminating paths subject to said path tracing analysis depending upon the signal value results of said simulation step at said designated inputs.
Claim 3
Dependent Claim
60 words
The method of claim 1 further comprising the step of performing a timing analysis of said digital circuit design using a hybrid path tracing analysis of said design from designated inputs to end points of signal propagation paths beginning at said designated inputs whenever the value of signals at said designated inputs varies as a result of said simulating step.
Claim 4
Dependent Claim
54 words
The method of claim 1 further wherein said performing step comprises determining a shortest and a longest delay path between said designated inputs and end points of said paths, and saving the violation history of only the two paths representing the longest and shortest paths from a designated input to a said end point.
Claim 5
Dependent Claim
53 words
The method of claim 1 further comprising the steps of inputting a user specified timing template to said apparatus, and setting input stimuli with regard to at least one of said designated inputs in accordance with said user specified timing template for determining the timing behavior of the digital circuit to be tested.
Claim 6
Dependent Claim
36 words
The method of claim 1 further comprising the step of providing for iteration of stimuli at designated inputs for checking the timing of a digital circuit design having a loop containing at least one transparent latch.
Claim 7
Independent Claim
101 words
A method for performing a timing analysis simulation upon a digital circuit design comprising the steps of inputting a user specified timing template, simulating a logical function evaluation of said design for each successive simulation time instance, performing a timing analysis of said digital circuit design using a hybrid path tracing analysis of said design from designated inputs to end points of signal propagation paths beginning at said designated inputs whenever the value of signals at said designated inputs varies as a result of said simulating step, and outputting the results of said time analysis for display to an end user.
Claim 8
Independent Claim
101 words
A method for performing a timing analysis simulation upon a digital circuit design comprising the steps of inputting a user specified timing template, simulating a logical function evaluation of said design for each successive simulation time instance, performing a timing analysis of said digital circuit design using a hybrid path tracing analysis of said design from designated inputs to end points of signal propagation paths beginning at said designated inputs whenever the value of signals at said designated inputs varies as a result of said simulating step, and outputting the results of said time analysis for display to an end user.
Claim 9
Dependent Claim
54 words
The method of claim 6 further wherein said performing step comprises determining a shortest and a longest delay path between said designated inputs and end points of said paths, and saving the violation history of only the two paths representing the longest and shortest paths from a designated input to a said end point.
Claim 10
Dependent Claim
54 words
The method of claim 6 further comprising the steps of inputting a user specified timing template to said apparatus, and setting the input stimuli with regard to at least one of said designated inputs in accordance with said user specified timing template for determining the timing behavior of the digital circuit to be tested.
Claim 11
Dependent Claim
36 words
The method of claim 6 further comprising the step of providing for iteration of stimuli at designated inputs for checking the timing of a digital circuit design having a loop containing at least one transparent latch.
Claim 12
Independent Claim
134 words
A method for performing a timing analysis simulation upon a digital circuit design comprising the steps of inputting said digital circuit design to an analysis system, simulating a logical function evaluation of said design for each of successive simulation time instants, performing a timing analysis of said digital circuit design using a path tracing analysis of said design from designated inputs to end points of signal propagation paths beginning at said inputs, said performing step comprising, determining a shortest and a longest delay path between said designated inputs and end points of said paths, and saving the timing violation history of only the two paths representing the longest and shortest paths from a designated input to a said end point, and displaying the timing violation history of the saved paths to an end user.
Claim 13
Independent Claim
134 words
A method for performing a timing analysis simulation upon a digital circuit design comprising the steps of inputting said digital circuit design to an analysis system, simulating a logical function evaluation of said design for each of successive simulation time instants, performing a timing analysis of said digital circuit design using a path tracing analysis of said design from designated inputs to end points of signal propagation paths beginning at said inputs, said performing step comprising, determining a shortest and a longest delay path between said designated inputs and end points of said paths, and saving the timing violation history of only the two paths representing the longest and shortest paths from a designated input to a said end point, and displaying the timing violation history of the saved paths to an end user.
Claim 14
Dependent Claim
54 words
The method of claim 10 further comprising the steps of inputting a user specified timing template to said apparatus, and setting the input stimuli with regard to at least one of said designated inputs in accordance with said user specified timing template for determining the timing behavior of the digital circuit to be tested.
Claim 15
Dependent Claim
36 words
The method of claim 10 further comprising the steps of providing for iteration of stimuli at designated inputs for checking the timing of a digital circuit design having a loop containing at least one transparent latch.
Claim 16
Independent Claim
135 words
A method for performing a timing analysis simulation upon a digital circuit design comprising the steps of inputting said digital circuit design to an analysis apparatus, inputting a user specified timing template to said apparatus, simulating a logical function evaluation of said design for each of successive simulation time instants, performing a timing analysis of said digital circuit design using a path tracing analysis of said design from designated inputs to end points of signal propagation paths beginning at said inputs, setting the input stimuli with regard to at least one of said designated inputs in accordance with said user specified timing template for determining the timing behavior of the digital circuit to be tested, and displaying the timing violation history of paths as a result of said timing analysis of said digital circuit design.
Claim 17
Independent Claim
135 words
A method for performing a timing analysis simulation upon a digital circuit design comprising the steps of inputting said digital circuit design to an analysis apparatus, inputting a user specified timing template to said apparatus, simulating a logical function evaluation of said design for each of successive simulation time instants, performing a timing analysis of said digital circuit design using a path tracing analysis of said design from designated inputs to end points of signal propagation paths beginning at said inputs, setting the input stimuli with regard to at least one of said designated inputs in accordance with said user specified timing template for determining the timing behavior of the digital circuit to be tested, and displaying the timing violation history of paths as a result of said timing analysis of said digital circuit design.
Claim 18
Dependent Claim
36 words
The method of claim 13 further comprising the step of providing for iteration of stimuli at designated inputs for checking the timing of a digital circuit design having a loop containing at least one transparent latch.
Claim 19
Independent Claim
114 words
A method for performing a timing analysis simulation upon a digital circuit design comprising the steps of inputting the digital circuit design to an analysis apparatus, simulating a logical function evaluation of said design for each of successive simulation time instants, performing a timing analysis of said digital circuit design using a path tracing analysis of said design from designated inputs to end points of signal propagation paths starting at said designated inputs, providing for iteration of stimuli at designated inputs for checking the timing of a digital circuit design having a loop containing at least one transparent latch, and displaying to an end user a timing violation history for said digital circuit design.
Claim 20
Independent Claim
114 words
A method for performing a timing analysis simulation upon a digital circuit design comprising the steps of inputting the digital circuit design to an analysis apparatus, simulating a logical function evaluation of said design for each of successive simulation time instants, performing a timing analysis of said digital circuit design using a path tracing analysis of said design from designated inputs to end points of signal propagation paths starting at said designated inputs, providing for iteration of stimuli at designated inputs for checking the timing of a digital circuit design having a loop containing at least one transparent latch, and displaying to an end user a timing violation history for said digital circuit design.
Claim 21
Independent Claim
277 words
A method for performing a timing analysis simulation upon a digital circuit design comprising the steps of inputting said digital circuit design to an analysis apparatus, simulating a logical function evaluation of said design for each of successive simulation time instants, performing a timing analysis of said digital circuit design using a path tracing analysis of said design from designated inputs to end points of signal propagation paths beginning at said designated inputs, eliminating paths subject to said path tracing analysis depending upon the signal value results of said simulation step at said designated inputs, said performing step comprising determining a shortest and a longest delay path between said designated inputs and end points of said paths, and saving the timing violation history of only the two paths representing the longest and shortest paths from a designated input to a said end point, performing a timing analysis of said digital circuit design using a hybrid path tracing analysis of said design from designated inputs to end points of signal propagation paths beginning at said designated inputs whenever the value of signals at said designated inputs varies as a result of said simulating step, inputting a user specified timing template to said apparatus, setting the input stimuli with regard to at least one of said designated inputs in accordance with said user specified timing template for determining the timing behavior of the digital circuit to be tested, providing for iteration of stimuli at designated inputs for checking the timing of a digital circuit design having a loop containing at least one transparent latch, and displaying to an end user a timing violation history for said digital circuit design.
Claim 22
Independent Claim
277 words
A method for performing a timing analysis simulation upon a digital circuit design comprising the steps of inputting said digital circuit design to an analysis apparatus, simulating a logical function evaluation of said design for each of successive simulation time instants, performing a timing analysis of said digital circuit design using a path tracing analysis of said design from designated inputs to end points of signal propagation paths beginning at said designated inputs, eliminating paths subject to said path tracing analysis depending upon the signal value results of said simulation step at said designated inputs, said performing step comprising determining a shortest and a longest delay path between said designated inputs and end points of said paths, and saving the timing violation history of only the two paths representing the longest and shortest paths from a designated input to a said end point, performing a timing analysis of said digital circuit design using a hybrid path tracing analysis of said design from designated inputs to end points of signal propagation paths beginning at said designated inputs whenever the value of signals at said designated inputs varies as a result of said simulating step, inputting a user specified timing template to said apparatus, setting the input stimuli with regard to at least one of said designated inputs in accordance with said user specified timing template for determining the timing behavior of the digital circuit to be tested, providing for iteration of stimuli at designated inputs for checking the timing of a digital circuit design having a loop containing at least one transparent latch, and displaying to an end user a timing violation history for said digital circuit design.
Claim 23
Dependent Claim
100 words
Apparatus for performing a timing analysis simulation upon a digital circuit design comprising means for inputting said digital circuit design to an analysis apparatus, means for simulating a logical function evaluation of said design for each of successive simulation time instants, means for performing a timing analysis of said digital circuit design using a path tracing analysis of said design from designated inputs to end points of signal propagation paths beginning at said designated inputs, and means for eliminating paths subject to said path tracing analysis depending upon the signal value results of said simulation step at said designated inputs.
Claim 24
Dependent Claim
100 words
Apparatus for performing a timing analysis simulation upon a digital circuit design comprising means for inputting said digital circuit design to an analysis apparatus, means for simulating a logical function evaluation of said design for each of successive simulation time instants, means for performing a timing analysis of said digital circuit design using a path tracing analysis of said design from designated inputs to end points of signal propagation paths beginning at said designated inputs, and means for eliminating paths subject to said path tracing analysis depending upon the signal value results of said simulation step at said designated inputs.
Claim 25
Dependent Claim
59 words
Apparatus according to claim 17 further comprising means for performing a timing analysis of said digital circuit design using a hybrid path tracing analysis of said design from designated inputs to end points of signal propagation paths beginning at said designated inputs whenever the value of signals at said designated inputs varies as a result of said simulating step.
Claim 26
Dependent Claim
57 words
Apparatus according to claim 17 wherein said performing means comprises means for determining a shortest and a longest delay path between said designated inputs and end points of said paths, and means for saving the violation history of only the two paths representing the longest and shortest paths from a designated input to a said end point.
Claim 27
Dependent Claim
52 words
Apparatus according to claim 17 further comprising means for inputting a user specified timing template, and means for setting the input stimuli with regard to at least one of said designated inputs in accordance with said user specified timing template for determining the timing behavior of the digital circuit to be tested.
Claim 28
Dependent Claim
32 words
Apparatus according to claim 17 further comprising means for providing for iteration of stimuli at designated inputs for checking the timing of a digital circuit design having a loop containing transparent latches.
Claim 29
Dependent Claim
108 words
Apparatus for performing a timing analysis simulation upon a digital circuit design comprising means for inputting said digital circuit design to an analysis apparatus, means for simulating a logical function evaluation of said design for each successive simulation time instance, means for performing a timing analysis of said digital circuit design using a hybrid path tracing analysis of said design from designated inputs to end points of signal propagation paths beginning at said designated inputs whenever the value of signals at said designated inputs varies as a result of said simulating step, and means for outputting the results of said time analysis for display to an end user.
Claim 30
Dependent Claim
108 words
Apparatus for performing a timing analysis simulation upon a digital circuit design comprising means for inputting said digital circuit design to an analysis apparatus, means for simulating a logical function evaluation of said design for each successive simulation time instance, means for performing a timing analysis of said digital circuit design using a hybrid path tracing analysis of said design from designated inputs to end points of signal propagation paths beginning at said designated inputs whenever the value of signals at said designated inputs varies as a result of said simulating step, and means for outputting the results of said time analysis for display to an end user.
Claim 31
Dependent Claim
57 words
Apparatus according to claim 22 wherein said performing means comprises means for determining a shortest and a longest delay path between said designated inputs and end points of said paths, and means for saving the violation history of only the two paths representing the longest and shortest paths from a designated input to a said end point.
Claim 32
Dependent Claim
52 words
Apparatus according to claim 22 further comprising means for inputting a user specified timing template, and means for setting the input stimuli with regard to at least one of said designated inputs in accordance with said user specified timing template for determining the timing behavior of the digital circuit to be tested.
Claim 33
Dependent Claim
32 words
Apparatus according to claim 22 further comprising means for providing for iteration of stimuli at designated inputs for checking the timing of a digital circuit design having a loop containing transparent latches.
Claim 34
Dependent Claim
143 words
Apparatus for performing a timing analysis simulation upon a digital circuit design comprising means for inputting said digital circuit design to the analysis apparatus, means for simulating a logical function evaluation of said design for each of successive simulation time instants, means for performing a timing analysis of said digital circuit design using a path tracing analysis of said design from designated inputs to end points of signal propagation paths beginning at said designated inputs, said performing means comprising means for determining a shortest and a longest delay path between said designated inputs and end points of said paths, and means for saving the timing violation history of only the two paths representing the longest and shortest paths from a designated input to a said end point, and means or displaying the timing violation history of the saved paths to an end user.
Claim 35
Dependent Claim
143 words
Apparatus for performing a timing analysis simulation upon a digital circuit design comprising means for inputting said digital circuit design to the analysis apparatus, means for simulating a logical function evaluation of said design for each of successive simulation time instants, means for performing a timing analysis of said digital circuit design using a path tracing analysis of said design from designated inputs to end points of signal propagation paths beginning at said designated inputs, said performing means comprising means for determining a shortest and a longest delay path between said designated inputs and end points of said paths, and means for saving the timing violation history of only the two paths representing the longest and shortest paths from a designated input to a said end point, and means or displaying the timing violation history of the saved paths to an end user.
Claim 36
Dependent Claim
52 words
Apparatus according to claim 26 further comprising means for inputting a user specified timing template, and means for setting the input stimuli with regard to at least one of said designated inputs in accordance with said user specified timing template for determining the timing behavior of the digital circuit to be tested.
Claim 37
Dependent Claim
32 words
Apparatus according to claim 26 further comprising means for providing for iteration of stimuli at designated inputs for checking the timing of a digital circuit design having a loop containing transparent latches.
Claim 38
Dependent Claim
140 words
Apparatus for performing a timing analysis simulation upon a digital circuit design comprising means for inputting said digital circuit design to said apparatus, means for inputting a user specified timing template, means for simulating a logical function evaluation of said design for each of successive simulation time instants, means for performing a timing analysis of said digital circuit design using a path tracing analysis of said design from designated inputs to end points of signal propagation paths beginning at said designated inputs, means for setting the input stimuli with regard to at least one of said designated inputs in accordance with said user specified timing template for determining the timing behavior of the digital circuit to be tested, and means for displaying the timing violation history of paths as a result of said timing analysis of said digital circuit design.
Claim 39
Dependent Claim
140 words
Apparatus for performing a timing analysis simulation upon a digital circuit design comprising means for inputting said digital circuit design to said apparatus, means for inputting a user specified timing template, means for simulating a logical function evaluation of said design for each of successive simulation time instants, means for performing a timing analysis of said digital circuit design using a path tracing analysis of said design from designated inputs to end points of signal propagation paths beginning at said designated inputs, means for setting the input stimuli with regard to at least one of said designated inputs in accordance with said user specified timing template for determining the timing behavior of the digital circuit to be tested, and means for displaying the timing violation history of paths as a result of said timing analysis of said digital circuit design.
Claim 40
Dependent Claim
32 words
Apparatus according to claim 29 further comprising means for providing for iteration of stimuli at designated inputs for checking the timing of a digital circuit design having a loop containing transparent latches.
Claim 41
Dependent Claim
116 words
Apparatus for performing a timing analysis simulation upon a digital circuit design comprising means for inputting the digital circuit design to said apparatus, means for simulating a logical function evaluation of said design for each of successive simulation time instants, means for performing a timing analysis of said digital circuit design using a path tracing analysis of said design from designated inputs to end points of signal propagation paths starting at said designated inputs, means for providing for iteration of stimuli at designated inputs for checking the timing of a digital circuit design having a loop containing transparent latches, and means for displaying to an end user a timing violation history for said digital circuit design.
Claim 42
Dependent Claim
116 words
Apparatus for performing a timing analysis simulation upon a digital circuit design comprising means for inputting the digital circuit design to said apparatus, means for simulating a logical function evaluation of said design for each of successive simulation time instants, means for performing a timing analysis of said digital circuit design using a path tracing analysis of said design from designated inputs to end points of signal propagation paths starting at said designated inputs, means for providing for iteration of stimuli at designated inputs for checking the timing of a digital circuit design having a loop containing transparent latches, and means for displaying to an end user a timing violation history for said digital circuit design.
Claim 43
Dependent Claim
289 words
Apparatus for performing a timing analysis simulation upon a digital circuit design comprising means for inputting said digital circuit design to an analysis apparatus, means for simulating a logical function evaluation of said design for each of successive simulation time instants, means for performing a timing analysis of said digital circuit design using a path tracing analysis of said design from designated inputs to end points of signal propagation paths beginning at said designated inputs, means for eliminating paths subject to said path tracing analysis depending upon the signal value results of said simulation step at said designated inputs, said performing means comprising means for determining a shortest and a longest delay path between said designated inputs and end points of said paths, and means for saving the timing violation history of only the two paths representing the longest and shortest paths from a designated input to a said end point, means for performing a timing analysis of said digital circuit design using a hybrid path tracing analysis of said design from designated inputs to end points of signal propagation paths beginning at said designated inputs whenever the value of signals at said designated inputs varies as a result of said simulating step, means for inputting a user specified timing template, means for setting the input stimuli with regard to at least one of said designated inputs n accordance with said user specified timing template for determining the timing behavior of the digital circuit to be tested, means for providing for iteration of stimuli at designated inputs for checking the timing of a digital circuit design having a loop containing transparent latches, and means for displaying to an end user a timing violation history for said digital circuit design.
Claim 44
Dependent Claim
289 words
Apparatus for performing a timing analysis simulation upon a digital circuit design comprising means for inputting said digital circuit design to an analysis apparatus, means for simulating a logical function evaluation of said design for each of successive simulation time instants, means for performing a timing analysis of said digital circuit design using a path tracing analysis of said design from designated inputs to end points of signal propagation paths beginning at said designated inputs, means for eliminating paths subject to said path tracing analysis depending upon the signal value results of said simulation step at said designated inputs, said performing means comprising means for determining a shortest and a longest delay path between said designated inputs and end points of said paths, and means for saving the timing violation history of only the two paths representing the longest and shortest paths from a designated input to a said end point, means for performing a timing analysis of said digital circuit design using a hybrid path tracing analysis of said design from designated inputs to end points of signal propagation paths beginning at said designated inputs whenever the value of signals at said designated inputs varies as a result of said simulating step, means for inputting a user specified timing template, means for setting the input stimuli with regard to at least one of said designated inputs n accordance with said user specified timing template for determining the timing behavior of the digital circuit to be tested, means for providing for iteration of stimuli at designated inputs for checking the timing of a digital circuit design having a loop containing transparent latches, and means for displaying to an end user a timing violation history for said digital circuit design.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-03-10 | 1995-09-09 | 1996-03-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-03-10 | 1999-09-09 | 2000-03-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-03-10 | 2003-09-09 | 2004-03-10 | $7700.00 | Window Closed / Lapsed |