US5103080A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Digitizer signal processing circuit for a bar code
Assignee: Symbol Technologies LLC
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Filing: 1990-12-10
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Granted: 1992-04-07
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Expires: 2010-12-10
Abstract
Abstract A signal processor digitizer circuit is disclosed for reading bar code symbols by detecting the times at which a scanning light spot moves from a space onto a bar code symbol or moved from a bar code signal onto a space. The novel signal processor digitizer circuit obtains all of its information for digitizing, false transition rejections, and margin cleaning from the first derivative of an analog signal produced by a photodetector detecting the scanning light spot. The original analog signal and a second derivative signal are not used which results in several advantages. Since the original analog signal is not needed, the signal differentiator circuit is placed at a very early stage in an amplifier string. Additional amplification stages can then be used to amplify the differentiated signal until it is large enough to be digitized. This results in two benefits. The differentiator circuit effectively filters out the effects of ambient light that could otherwise cause the last amplifier stage to saturate, thereby improving ambient light immunity. It also eliminates the transient response of other forms of high pass filtering or AC coupling that are ordinarily required to improve ambient light immunity or to eliminate the build-up of large offset voltages associated with DC coupled amplifiers.
Inventors
- 👤 Edward Barkan
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 13:36
CPC Classifications
G; G06; G06K; G06K7/00; G06K7/10; G06K7/10544; G06K7/10821; G06K7/10851
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
275 words
A signal processor digitizer circuit for detecting the time at which a scanning light spot moves from a space onto a bar code symbol or moves from a ar code symbol onto a space, comprising: a) a photodetector means for sensing a scanning light spot scanned across and reflected by a bar code and generating an analog signal representative thereof; b) a differentiator circuit means receiving the analog signal as an input and generating a first derivative signal of the analog signal; c) a delay circuit means receiving the first derivative signal as an input and generating a delayed first derivative signal; d) a peak locating comparator circuit means receiving the first derivative signal as a first input and the delayed first derivative signal as a second input, and detecting crossings of the first derivative signal and the delayed first derivative signal when the signals are equal, which result in transitions in the output signal of the peak locating comparator circuit means; e) a false transition gating circuit means for discriminating against false transitions in the output signal of the peak locating comparator circuit means and changing states only upon the detection of transitions in the output signal of the peak locating comparator circuit means about a given threshold; and f) an output circuit means receiving a first input from the peak locating comparator circuit means and a second input from the false transition gating circuit means, and changing the state of its output signal only if the false transition gating circuit means has changed state since the last change of state of the peak locating comparator circuit means to discriminate against false transition signals.
Claim 2
Dependent Claim
275 words
A signal processor digitizer circuit for detecting the time at which a scanning light spot moves from a space onto a bar code symbol or moves from a ar code symbol onto a space, comprising: a) a photodetector means for sensing a scanning light spot scanned across and reflected by a bar code and generating an analog signal representative thereof; b) a differentiator circuit means receiving the analog signal as an input and generating a first derivative signal of the analog signal; c) a delay circuit means receiving the first derivative signal as an input and generating a delayed first derivative signal; d) a peak locating comparator circuit means receiving the first derivative signal as a first input and the delayed first derivative signal as a second input, and detecting crossings of the first derivative signal and the delayed first derivative signal when the signals are equal, which result in transitions in the output signal of the peak locating comparator circuit means; e) a false transition gating circuit means for discriminating against false transitions in the output signal of the peak locating comparator circuit means and changing states only upon the detection of transitions in the output signal of the peak locating comparator circuit means about a given threshold; and f) an output circuit means receiving a first input from the peak locating comparator circuit means and a second input from the false transition gating circuit means, and changing the state of its output signal only if the false transition gating circuit means has changed state since the last change of state of the peak locating comparator circuit means to discriminate against false transition signals.
Claim 3
Dependent Claim
79 words
A signal processor digitizer circuit as claimed in claim 1, wherein said output circuit means further includes a margin threshold detecting circuit receiving the first derivative signal as an input and functioning as a retriggerable one shot circuit which does not time out as long as the first derivative signal includes a series of pulses that exceed the threshold of the margin threshold detecting circuit, but upon time out prevents the output circuit means from passing an output signal.
Claim 4
Dependent Claim
37 words
A signal processor digitizer circuit as claimed in claim 2, wherein the level at which said false transition gating circuit means exceeds a threshold is determined by the level of hysteresis resulting from a positive feedback therein.
Claim 5
Dependent Claim
38 words
A signal processor digitizer circuit as claimed in claim 3, further including an amplifier with low pass filtering coupled to the output of said differentiator circuit means and amplification and low pass filtering for the first derivative signal.
Claim 6
Dependent Claim
37 words
A signal processor digitizer circuit as claimed in claim 1, wherein the level at which said false transition gating circuit means exceeds a threshold is determined by the level of hysteresis resulting from a positive feedback therein.
Claim 7
Dependent Claim
39 words
A signal processor digitizer circuit as claimed in claim 1, further including an amplifier with low pass filtering coupled to the output of said differentiator circuit means and providing amplification and low pass filtering for the first derivative signal.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-04-07 | 1995-10-07 | 1996-04-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-04-07 | 1999-10-07 | 2000-04-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-04-07 | 2003-10-07 | 2004-04-07 | $7700.00 | Window Closed / Lapsed |