MOS transistor with a charge induced drain extension

Claim 1

A method for forming a semiconductor device comprising the steps of: forming a gate dielectric layer on the surface of a first semiconductor region of a first conductivity type; forming a gate electrode on said gate dielectric layer, thereby defining a channel region located within said first semiconductor region beneath said gate electrode; forming a first source/drain region having a second conductivity type opposite said first conductivity type, located within said first semiconductor region, below and subjacent to said gate electrode; forming a second source/drain region having a second conductivity type opposite said first conductivity type, located within said first semiconductor region, below and laterally spaced apart from said gate electrode, thereby leaving a gap between said channel region and said second source/drain region; and forming a charge by utilizing a dopant comprising a group I, group II, group IV, or group VII element stored essentially in said gate dielectric layer above said gap thereby forming a source/drain extension region located within said first semiconductor region below and adjacent to said gate electrode, said source/drain extension region being located in that portion of said first semiconductor region between said second source/drain region and said channel region, said source/drain extension being inverted so as to be of a second conductivity type opposite said first conductivity type due to the presence of said charge.

Claim 2

A method for forming a semiconductor device comprising the steps of: forming a gate dielectric layer on the surface of a first semiconductor region of a first conductivity type; forming a gate electrode on said gate dielectric layer, thereby defining a channel region located within said first semiconductor region beneath said gate electrode; forming a first source/drain region having a second conductivity type opposite said first conductivity type, located within said first semiconductor region, below and subjacent to said gate electrode; forming a second source/drain region having a second conductivity type opposite said first conductivity type, located within said first semiconductor region, below and laterally spaced apart from said gate electrode, thereby leaving a gap between said channel region and said second source/drain region; and forming a charge by utilizing a dopant comprising a group I, group II, group IV, or group VII element stored essentially in said gate dielectric layer above said gap thereby forming a source/drain extension region located within said first semiconductor region below and adjacent to said gate electrode, said source/drain extension region being located in that portion of said first semiconductor region between said second source/drain region and said channel region, said source/drain extension being inverted so as to be of a second conductivity type opposite said first conductivity type due to the presence of said charge.

Claim 14

A method for forming a semiconductor device comprising the steps of: forming a gate dielectric layer on the surface of a first semiconductor region having a first conductivity type; forming a gate electrode on said gate dielectric layer, thereby defining a channel region located within said first semiconductor region beneath said gate electrode; forming a source region having a second conductivity type opposite said first conductivity type, located within said first semiconductor region, below and laterally spaced apart from said gate electrode, thereby leaving a first gap between said channel region and said source region; forming a drain region having a second conductivity type opposite said first conductivity type, located within said first semiconductor region, below and laterally spaced apart from said gate electrode, thereby leaving a second gap between said channel region and said drain region; and forming a first charge by utilizing a dopant comprising a group I, group II, group VI, or group VII element stored essentially in said gate dielectric layer above said first gap, thereby forming a source extension region located within said first semiconductor region below and adjacent to said gate electrode, said source extension region being located in the portion of said first semiconductor region between said source region and said channel region, said source extension being inverted so as to be of a second conductivity type opposite said first conductivity type due to the presence of said first charge; and forming a second charge by utilizing a dopant comprising a group I, group II, group VI, or group VII element stored essentially in said gate dielectric layer above said second gap, thereby forming a drain extension region located within said first semiconductor region below and adjacent to said gate electrode, said drain extension region being located in that portion of said first semiconductor region between said drain region and said channel region, said drain extension being inverted so as to be of a second conductivity type opposite said first conductivity type due to the presence of said second charge.

Claim 15

A method for forming a semiconductor device comprising the steps of: forming a gate dielectric layer on the surface of a first semiconductor region having a first conductivity type; forming a gate electrode on said gate dielectric layer, thereby defining a channel region located within said first semiconductor region beneath said gate electrode; forming a source region having a second conductivity type opposite said first conductivity type, located within said first semiconductor region, below and laterally spaced apart from said gate electrode, thereby leaving a first gap between said channel region and said source region; forming a drain region having a second conductivity type opposite said first conductivity type, located within said first semiconductor region, below and laterally spaced apart from said gate electrode, thereby leaving a second gap between said channel region and said drain region; and forming a first charge by utilizing a dopant comprising a group I, group II, group VI, or group VII element stored essentially in said gate dielectric layer above said first gap, thereby forming a source extension region located within said first semiconductor region below and adjacent to said gate electrode, said source extension region being located in the portion of said first semiconductor region between said source region and said channel region, said source extension being inverted so as to be of a second conductivity type opposite said first conductivity type due to the presence of said first charge; and forming a second charge by utilizing a dopant comprising a group I, group II, group VI, or group VII element stored essentially in said gate dielectric layer above said second gap, thereby forming a drain extension region located within said first semiconductor region below and adjacent to said gate electrode, said drain extension region being located in that portion of said first semiconductor region between said drain region and said channel region, said drain extension being inverted so as to be of a second conductivity type opposite said first conductivity type due to the presence of said second charge.

Claim 27

A method for forming a semiconductor device comprising the steps of: forming a gate dielectric layer on the surface of a first semiconductor region having a first conductivity type; forming a gate electrode on said gate dielectric layer, thereby defining a channel region located within said first semiconductor region beneath said gate electrode, and defining a source and a drain region located within said first semiconductor region on opposite sides of said channel region; forming a charge by utilizing a dopant comprising a group I, group II, group VI, or group VII element stored n said gate dielectric layer above a selected one or both of said source and drain regions, thereby forming a lightly doped source and/or drain region which are inverted so as to be of a second conductivity type opposite said first conductivity type due to the presence of said charge; following said step of forming a charge, forming oxide sidewall spacers on the source and/or drain sides of said gate electrode; and following said step of forming oxide sidewall spacers, implanting dopants of said second conductivity type to said source and drain regions where not protected by said sidewall spacers, wherein said lightly doped regions serve as source and/or drain extension regions between said channel region and said highly doped source and/or drain regions, respectively.

Claim 28

A method for forming a semiconductor device comprising the steps of: forming a gate dielectric layer on the surface of a first semiconductor region having a first conductivity type; forming a gate electrode on said gate dielectric layer, thereby defining a channel region located within said first semiconductor region beneath said gate electrode, and defining a source and a drain region located within said first semiconductor region on opposite sides of said channel region; forming a charge by utilizing a dopant comprising a group I, group II, group VI, or group VII element stored n said gate dielectric layer above a selected one or both of said source and drain regions, thereby forming a lightly doped source and/or drain region which are inverted so as to be of a second conductivity type opposite said first conductivity type due to the presence of said charge; following said step of forming a charge, forming oxide sidewall spacers on the source and/or drain sides of said gate electrode; and following said step of forming oxide sidewall spacers, implanting dopants of said second conductivity type to said source and drain regions where not protected by said sidewall spacers, wherein said lightly doped regions serve as source and/or drain extension regions between said channel region and said highly doped source and/or drain regions, respectively.

Claim 40

A method for forming a semiconductor device comprising the steps of: forming a gate dielectric layer on the surface of a first semiconductor region of a first conductivity type; forming a gate electrode on said gate dielectric layer, thereby defining a channel region located within said first semiconductor region beneath said gate electrode; forming a first source/drain region having a second conductivity type opposite said first conductivity type, located within said first semiconductor region; forming a second source/drain region having a second conductivity type opposite said first conductivity type, located within said first semiconductor region, wherein one or both of said source and drain regions are formed below and laterally spaced apart form said gate electrode, thereby leaving an associated first and/or second gap between said channel region and the respective source/drain region; and forming a charge by utilizing a dopant comprising a group I, group II, group VI, or group VII element stored essentially in said gate dielectric layer above each of said gaps thereby forming a first and/or a second source/drain extension region located within said first semiconductor region below and adjacent to said gate electrode, and source/drain extension regions being located in that portion of said first semiconductor region between a respective one of said source/drain regions and said channel region, said source/drain regions and said channel region, said source/drain extension regions being inverted so as to be of a second conductivity type opposite said first conductivity type due to the presence of said charge.

Claim 41

A method for forming a semiconductor device comprising the steps of: forming a gate dielectric layer on the surface of a first semiconductor region of a first conductivity type; forming a gate electrode on said gate dielectric layer, thereby defining a channel region located within said first semiconductor region beneath said gate electrode; forming a first source/drain region having a second conductivity type opposite said first conductivity type, located within said first semiconductor region; forming a second source/drain region having a second conductivity type opposite said first conductivity type, located within said first semiconductor region, wherein one or both of said source and drain regions are formed below and laterally spaced apart form said gate electrode, thereby leaving an associated first and/or second gap between said channel region and the respective source/drain region; and forming a charge by utilizing a dopant comprising a group I, group II, group VI, or group VII element stored essentially in said gate dielectric layer above each of said gaps thereby forming a first and/or a second source/drain extension region located within said first semiconductor region below and adjacent to said gate electrode, and source/drain extension regions being located in that portion of said first semiconductor region between a respective one of said source/drain regions and said channel region, said source/drain regions and said channel region, said source/drain extension regions being inverted so as to be of a second conductivity type opposite said first conductivity type due to the presence of said charge.