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US5114873A
Expired / Lapsed
US
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Method for manufacturing a stacked capacitor DRAM cell
Assignee: Samsung Electronics Co Ltd
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Filing: 1990-10-04
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Granted: 1992-05-19
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Expires: 2010-10-04
Abstract
Abstract The method comprises the steps of: forming the transistor on a substrate and then depositing an interlayer insulating layer, and forming a design pattern of a first conductive layer by vertically etching it using a mask; horizontally overetching the pattern by using the etching process used for forming the pattern; depositing a first insulating film and then depositing the second conductive layer to the thickness needed to protect the first insulating film; vertically etching the second conductive layer, first insulating film and interlayer insulating layer by applying the mask used in vertically etching the first conductive layer; additionally depositing the second conductive layer; forming a design pattern of the second conductive layer by vertically etching it using a mask; horizontally overetching the pattern of the second conductive layer; depositing the second insulating film and then depositing a third conductive layer to have the thickness to protect the second insulating film; vertically etching the third conductive layer and second insulating film by applying the etching mask of the second conductive layer; additionally depositing the third conductive layer. The method attains larger effective capacitance in which a plate electrode layer surrounds even the lower surface of a storage electrode layer of the stack capacitor without using any extra mask.
Inventors
- 👤 Kyung-hun Kim
- 👤 Seong-tae Kim
- 👤 Hyeong-kyu Lee
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 00:24
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/01; H10B12/02; H10B12/03; H10B12/033
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
403 words
A method for manufacturing a semiconductor device having a plurality of memory cells, each of which consists of a transistor and a stack capacitor, said method comprising the steps of: (a) forming said transistor on a surface of a semiconductor substrate; (b) depositing an interlayer insulating layer on the surface of said substrate whereon the transistor has been formed in step (a); (c) depositing a first conductive layer on the surface of said substrate whereon the interlayer insulating layer has been deposited in step (b); (d) forming a design pattern on the first conductive layer by vertically etching an etching pattern from a mask onto the first conductive layer; (e) horizontally overetching the design pattern on the first conductive layer formed in step (d) by a wet etching process, using the etching pattern of step (d); (f) depositing a first thin insulating film on the surface of the substrate whereon the first conductive layer has been horizontally overetched in step (e), (g) depositing a second conductive layer on the first thin insulating film to provide sufficient thickness to protect the first insulating film; (h) vertically etching the second conductive layer, the first thin insulating film and the interlayer insulating layer with the mask used in etching the first conductive layer in step (d), wherein a first contact hole is formed to contact the transistor; (i) depositing a predetermined thickness of a material used in the second conductive layer on the surface of the substrate whereon the contact hole has been formed in step (h); (j) forming a design pattern by vertically etching an etching pattern from a mask onto the second conductive layer; (k) horizontally overetching the second conductive layer by a wet etching process, using the etching pattern of step (j); (l) depositing a thin second insulating film on the whole surface of the structure after removing the second conductive layer; (m) depositing a sufficient thickness of a third conductive layer to protect the second insulating film; (n) partially exposing a surface of the first conductive layer by vertically etching the third conductive layer and the thin second insulating film by applying the mask used in etching the second conductive layer in step (j); and (o) depositing a predetermined thickness of a material used in the third conductive layer on the surface of the substrate partially exposed in step (n) so that a surface of the first conductive layer is partially exposed.
Claim 2
Independent Claim
403 words
A method for manufacturing a semiconductor device having a plurality of memory cells, each of which consists of a transistor and a stack capacitor, said method comprising the steps of: (a) forming said transistor on a surface of a semiconductor substrate; (b) depositing an interlayer insulating layer on the surface of said substrate whereon the transistor has been formed in step (a); (c) depositing a first conductive layer on the surface of said substrate whereon the interlayer insulating layer has been deposited in step (b); (d) forming a design pattern on the first conductive layer by vertically etching an etching pattern from a mask onto the first conductive layer; (e) horizontally overetching the design pattern on the first conductive layer formed in step (d) by a wet etching process, using the etching pattern of step (d); (f) depositing a first thin insulating film on the surface of the substrate whereon the first conductive layer has been horizontally overetched in step (e), (g) depositing a second conductive layer on the first thin insulating film to provide sufficient thickness to protect the first insulating film; (h) vertically etching the second conductive layer, the first thin insulating film and the interlayer insulating layer with the mask used in etching the first conductive layer in step (d), wherein a first contact hole is formed to contact the transistor; (i) depositing a predetermined thickness of a material used in the second conductive layer on the surface of the substrate whereon the contact hole has been formed in step (h); (j) forming a design pattern by vertically etching an etching pattern from a mask onto the second conductive layer; (k) horizontally overetching the second conductive layer by a wet etching process, using the etching pattern of step (j); (l) depositing a thin second insulating film on the whole surface of the structure after removing the second conductive layer; (m) depositing a sufficient thickness of a third conductive layer to protect the second insulating film; (n) partially exposing a surface of the first conductive layer by vertically etching the third conductive layer and the thin second insulating film by applying the mask used in etching the second conductive layer in step (j); and (o) depositing a predetermined thickness of a material used in the third conductive layer on the surface of the substrate partially exposed in step (n) so that a surface of the first conductive layer is partially exposed.
Claim 3
Dependent Claim
30 words
A method for manufacturing a semiconductor device as set forth in claim 1, wherein said first and second insulating films are formed by laminating thermal oxide films and nitride films.
Claim 4
Dependent Claim
28 words
A method for manufacturing a semiconductor device as set forth in claim 2, wherein said first to third conductive layers are comprised of polycrystalline silicon doped with impurity.
Claim 5
Dependent Claim
28 words
A method for manufacturing a semiconductor device as set forth in claim 3, wherein said first and second insulating films are from 60 to 80 Å in thickness.
Claim 6
Dependent Claim
38 words
A method for manufacturing a semiconductor device as set forth in claim 4, wherein the thicknesses of the first and third conductive layers are from about 300 to 500 Å, sufficient protect said first and second insulating films.
Claim 7
Dependent Claim
31 words
A method for manufacturing a semiconductor device as set forth in claim 5, wherein the predetermined thicknesses of the first and third conductive layers are from about 1500 to 2000 Å.
Claim 8
Dependent Claim
20 words
A method for manufacturing a semiconductor device as set forth in claim 1, wherein said transistor is a MOS transistor.
Claim 9
Dependent Claim
93 words
A method for manufacturing a semiconductor device as set forth in claim 7, wherein said method additionally comprises the steps of: depositing a layer of BPSG film on the whole surface of said third conductive layer; vertically etching said layer of BPSG film, the third and the first conductive layers and the interlayer insulating film, so as to form the second contact hole in order to contact said transistor; and forming a bit line of said memory cell on the structure whereon said second contact hole is located by using a metallization process.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-05-19 | 1995-11-18 | 1996-05-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-05-19 | 1999-11-18 | 2000-05-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-05-19 | 2003-11-18 | 2004-05-19 | $7700.00 | Window Closed / Lapsed |