Dma controller having programmable logic array for outputting control information required during a next transfer cycle during one transfer cycle

Claim 1

A direct memory access controller coupled to a system data bus for controlling a data transfer by a direct memory access, said direct memory access controller comprising: internal bus means for providing a data communication path between elements of the controller; data handler means, coupled to the system data bus and said internal bus means, for controlling an exchange of data between the system data bus and said internal bus means; microsequencer means, coupled to said data handler means and said internal bus means, said microsequencer for controlling the direct memory access controller in units of one system clock cycle during one present transfer cycle in accordance with a microprogram; arithmetic logic unit means, coupled to said internal bus means, for outputting a next transfer address and a byte count which indicates how many bytes of data remain to be transferred; request handler means, coupled to said microsequencer means, for receiving an external transfer request and for supplying the external transfer request to a programmable logic array means; and programmable logic array means coupled to an output of said microsequencer means, and supplied with the transfer request, transfer mode information and at least portions of the transfer address and the byte count, said programmable logic array means also being coupled to said internal bus means, and is for outputting control information required during a next transfer cycle during one transfer cycle which corresponds to a predetermined number of system clock cycles based on the output of said microsequencer means, wherein data transfers between an input/output device and a memory device is controlled by microprograms of said microsequencer means in cooperation with output signals from said programmable logic array means.