US5137839A
Expired / Lapsed
US
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Method of manufacturing a bipolar transistor having polysilicon layer which serves as an emitter electrode and passivating dangling bonds
Assignee: Toshiba Corp
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Filing: 1991-05-24
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Granted: 1992-08-11
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Expires: 2011-05-24
Abstract
Abstract In a bipolar transistor, a polysilicon layer formed on an emitter diffusion layer is used as an emitter electrode. After the polysilicon layer is formed, an atom is introduced into the polysilicon layer. A thermal treatment is then performed, and the atom is combined with a dangling bond of a silicon atom existing on a crystal grain interface of the polysilicon layer, thereby passivating the dangling bond of the silicon atom.
Inventors
- 👤 Youchiro Niitsu
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 20:28
CPC Classifications
H; H10; H10D; H10D10/00; H10D10/01; H10D10/051; H10D64/00; H10D64/01; H10D64/011; H10D64/0111; H10D64/0113; H10P; H10P32/00; H10P32/30; H10P32/302; Y; Y10; Y10S; Y10S148/00; Y10S148/01; Y10S438/00; Y10S438/91
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
137 words
A method of manufacturing a semiconductor device, comprising the steps of: forming a bipolar transistor having a polysilicon layer formed on an emitter diffusion layer and serving as an emitter electrode; introducing at least one of a fluorine atom and a hydrogen atom into the polysilicon layer; covering the polysilicon layer with an interlayer insulation film; and performing a thermal treatment (i) to combine a silicon atom having a dangling bond which exists on a crystal grain interface of the polysilicon layer with said at least one of the fluorine atom and the hydrogen atom, thereby passivating the dangling bond of the silicon atom, and (ii) to lower an interface trap charge density on the crystal grain interface of the polysilicon layer, thereby preventing minority carriers on the crystal grain interface from being recombined with one another.
Claim 2
Independent Claim
137 words
A method of manufacturing a semiconductor device, comprising the steps of: forming a bipolar transistor having a polysilicon layer formed on an emitter diffusion layer and serving as an emitter electrode; introducing at least one of a fluorine atom and a hydrogen atom into the polysilicon layer; covering the polysilicon layer with an interlayer insulation film; and performing a thermal treatment (i) to combine a silicon atom having a dangling bond which exists on a crystal grain interface of the polysilicon layer with said at least one of the fluorine atom and the hydrogen atom, thereby passivating the dangling bond of the silicon atom, and (ii) to lower an interface trap charge density on the crystal grain interface of the polysilicon layer, thereby preventing minority carriers on the crystal grain interface from being recombined with one another.
Claim 3
Dependent Claim
19 words
The method according to claim 1, wherein said atom is introduced into said polysilicon layer using an ion-implantation method.
Claim 4
Dependent Claim
21 words
The method according to claim 1, wherein said atom is introduced into said polysilicon layer using a vapor phase diffusion method.
Claim 5
Dependent Claim
245 words
The method according to claim 1, wherein said step of forming the bipolar transistor comprises the steps of: introducing an impurity of a second conductivity type into a major surface of a semiconductor substrate of a first conductivity type; forming an epitaxial layer of the second conductivity type on said semiconductor substrate and diffusing the impurity of the second conductivity type into said semiconductor substrate and said epitaxial layer to form a buried layer; selectively forming a field insulation film on said epitaxial layer; forming a first impurity diffusion layer of the second conductivity type in said epitaxial layer to such a depth as to reach said buried layer; forming a second impurity diffusion layer of the first conductivity type serving as an inner base in said epitaxial layer away from said first impurity diffusion layer; forming a third impurity diffusion layer of the first conductivity type serving as an outer base in said epitaxial layer away from said first impurity diffusion layer and in contact with said second impurity diffusion layer; forming an insulation film on a resultant structure; forming an opening in said insulation film on part of said second impurity diffusion layer; forming a polysilicon layer on said insulation film and in said opening; introducing an impurity of the second conductivity type into said polysilicon layer; and forming an emitter diffusion layer of the second conductivity type in said second impurity diffusion layer while using said polysilicon layer as a diffusion source.
Claim 6
Dependent Claim
56 words
The method according to claim 4, further comprising a step of forming an isolation region of the first conductivity type in said epitaxial layer to such a depth as to reach the major surface of said semiconductor substrate after said step of forming the epitaxial layer of the second conductivity type and forming the buried layer.
Claim 7
Dependent Claim
61 words
The method according to claim 1, wherein said step of introducing the impurity of the second conductivity type into said polysilicon layer comprises a step of ion-implanting an impurity of the second conductivity type into said polysilicon layer, a step of forming an insulation film on said polysilicon layer, and a step of diffusing the ion-implanted impurity by a thermal treatment.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-08-11 | 1996-02-10 | 1996-08-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-08-11 | 2000-02-10 | 2000-08-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-08-11 | 2004-02-10 | 2004-08-11 | $7700.00 | Window Closed / Lapsed |