US5140681A
Expired / Lapsed
US
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Multi-processing system and cache apparatus for use in the same
Assignee: Hitachi Ltd
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Filing: 1989-05-23
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Granted: 1992-08-18
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Expires: 2009-05-23
Abstract
Abstract A main memory is subdivided into a shared region to undergo a write access from a plurality of processors and an input/output device and a plurality of private regions to undergo a write access only from the associated processor. Each of the cache devices includes a region discriminating circuit for determining whether an address generated from the processor is to be employed for an access to the shared region or to the private regions. If the access is to be conducted to the shared region, the cache devices operate according to the write-through method. On the other hand, if the access is to be conducted to the private region, the cache devices operate according to the copy-back method. When the processor or the input/output device rewrites data in the shared region of the main memory, the stored data of the shared region in the cache device of the processor is invalidated.
Inventors
- 👤 Kunio Uchiyama
- 👤 Hirokazu Aoki
- 👤 Susumu Hatano
- 👤 Kanji Oishi
- 👤 Takashi Kikuchi
- 👤 Hiroshi Fukuta
- 👤 Yasuhiko Saigou
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 14:20
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/22; G06F9/28; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0806; G06F12/0815; G06F2212/00; G06F2212/62; G06F2212/621
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
255 words
A multi-processing system comprising: (1) a first processor and a second processor each for generating an address; (2) a bus; (3) a main memory coupled to said bus; (4) an input/output device coupled to said bus; (5) a first cache device coupled between said first processor and said bus; and (6) a second cache device coupled between said second processor and said bus wherein: said main memory is subdivided into a shared region to undergo a write access from said first processor, said second processor, and said input/output device and private regions to undergo a write access from said first processor or said second processor; and each of said first and second cache devices includes: (a) a region discriminating circuit for determining whether an address generated from said first or second processor is to be employed for an access to the shared region or to the private region; and (b) a cache control circuit for controlling a data store operation on said cache devices and on said main memory in response to an output from said region discriminating circuit, the output from said region discriminating circuit causing, when the address generated from said first or second processor is used to access the shared region, said cache devices to effect a data write operation in a write-through method, the output from said region discriminating circuit causing, when the address generated from said first or second processor is used to access the private region, said cache devices to effect a data write operation in a copy-back method.
Claim 2
Dependent Claim
255 words
A multi-processing system comprising: (1) a first processor and a second processor each for generating an address; (2) a bus; (3) a main memory coupled to said bus; (4) an input/output device coupled to said bus; (5) a first cache device coupled between said first processor and said bus; and (6) a second cache device coupled between said second processor and said bus wherein: said main memory is subdivided into a shared region to undergo a write access from said first processor, said second processor, and said input/output device and private regions to undergo a write access from said first processor or said second processor; and each of said first and second cache devices includes: (a) a region discriminating circuit for determining whether an address generated from said first or second processor is to be employed for an access to the shared region or to the private region; and (b) a cache control circuit for controlling a data store operation on said cache devices and on said main memory in response to an output from said region discriminating circuit, the output from said region discriminating circuit causing, when the address generated from said first or second processor is used to access the shared region, said cache devices to effect a data write operation in a write-through method, the output from said region discriminating circuit causing, when the address generated from said first or second processor is used to access the private region, said cache devices to effect a data write operation in a copy-back method.
Claim 3
Dependent Claim
52 words
A multi-processing system according to claim 1 wherein said cache control circuit associated with said first cache device includes means responsive to said second processor or said input/output device rewriting data in the shared region of said main memory for invalidating stored data of the shared region in said first cache device.
Claim 4
Dependent Claim
257 words
A cache apparatus to be employed in a multi-processing system comprising first and second processors each for generating an address, a bus, a main memory coupled to said bus, and an input/output device coupled to said bus, said main memory being subdivided into a shared region to undergo a write access from said first processor, said second processor, and said input/output device and private regions to undergo a write access from said first processor or said second processor wherein: said cache apparatus includes a first cache device coupled between said first processor and said bus and a second cache device coupled between said second processor and said bus; each of said first and second cache devices including: (a) a region discriminating circuit for determining whether an address generated from said first or second processor is to be employed for an access to the shared region or to the private region; and (b) a cache control circuit for controlling a data store operation on said cache devices and on said main memory in response to an output from said region discriminating circuit, the output from said region discriminating circuit causing, when the address generated from said first or second processor is used to access the shared region, said cache devices to effect a data write operation in a write-through method, the output from said region discriminating circuit causing, when the address generated from said first or second processor is used to access the private region, said cache devices to effect a data write operation in a copy-back method.
Claim 5
Dependent Claim
257 words
A cache apparatus to be employed in a multi-processing system comprising first and second processors each for generating an address, a bus, a main memory coupled to said bus, and an input/output device coupled to said bus, said main memory being subdivided into a shared region to undergo a write access from said first processor, said second processor, and said input/output device and private regions to undergo a write access from said first processor or said second processor wherein: said cache apparatus includes a first cache device coupled between said first processor and said bus and a second cache device coupled between said second processor and said bus; each of said first and second cache devices including: (a) a region discriminating circuit for determining whether an address generated from said first or second processor is to be employed for an access to the shared region or to the private region; and (b) a cache control circuit for controlling a data store operation on said cache devices and on said main memory in response to an output from said region discriminating circuit, the output from said region discriminating circuit causing, when the address generated from said first or second processor is used to access the shared region, said cache devices to effect a data write operation in a write-through method, the output from said region discriminating circuit causing, when the address generated from said first or second processor is used to access the private region, said cache devices to effect a data write operation in a copy-back method.
Claim 6
Dependent Claim
52 words
A multi-processing system according to claim 3 wherein said cache control circuit associated with said first cache device includes means responsive to said second processor or said input/output device rewriting data in the shared region of said main memory for invalidating stored data of the shared region in said first cache device.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-08-18 | 1996-02-17 | 1996-08-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-08-18 | 2000-02-17 | 2000-08-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-08-18 | 2004-02-17 | 2004-08-18 | $7700.00 | Window Closed / Lapsed |