Semiconductor device process using diffusant penetration and source layers for shallow regions

Claim 2

A process for fabricating a semiconductor device comprising the steps of: providing a semiconductor substrate having a surface; forming a first oxide layer of a first predetermined thickness on a selected portion of the substrate surface; forming a first layer of polycrystalline silicon doped with boron dopant impurities overlaying the first oxide layer; annealing the first layer of polycrystalline silicon to cause a portion of the boron dopant impurities to diffuse through the oxide layer and into the semiconductor substrate to form a doped region in the semiconductor substrate; removing the first layer of polycrystalline silicon and the first oxide layer; forming a second oxide layer of a second predetermined thickness on the selected portion of the substrate surface overlaying the doped region, the second predetermined thickness being substantially less than the first predetermined thickness; depositing a second layer of polycrystalline silicon on the second insulating layer.

Claim 3

The process of claim 1 wherein the semiconductor substrate is of N type conductivity and wherein the step of forming the first layer of polycrystalline silicon comprises the steps of: depositing a layer of undoped polycrystalline silicon; and implanting the layer of undoped polycrystalline silicon with boron containing ions.

Claim 4

The process of claim 2 further comprising the step of: doping the second layer of polycrystalline silicon with N type dopant impurities.

Claim 5

The process of claim 3 further comprising the steps of: patterning the second layer of polycrystalline silicon to form a gate electrode overlaying the doped region; and forming P type source and drain regions in the semiconductor substrate in alignment with the gate electrode.

Claim 6

The process of claim 2 wherein the step of implanting comprises implanting with BF 2 ions.

Claim 7

The process of claim 1 wherein the step of forming a first oxide layer comprises forming a silicon oxide layer having a thickness of about 10-15 nanometers.

Claim 8

The process of claim 6 wherein the step of forming a silicon oxide layer comprises chemical vapor depositing a silicon dioxide layer.

Claim 9

The process of claim 1 wherein the step of forming a second insulating layer comprises the step of growing a thermal silicon dioxide layer by rapid thermal oxidation.

Claim 10

The process of claim 1 wherein the step of forming a second insulating layer comprises the step of depositing silicon oxide by low pressure chemical vapor deposition.

Claim 11

The process of claim 1 further comprising the steps of: forming a capping layer of oxide overlaying the first layer of polycrystalline silicon; and forming a layer of silicon nitride overlaying the layer of capping oxide.

Claim 12

A process for fabricating a P channel MOS transistor comprising the steps of: providing a semiconductor substrate having a surface region of N type conductivity; forming a first oxide layer having a thickness of about 10-15 nanometers overlying the surface region; forming an undoped first layer of polycrystalline silicon overlaying the first oxide layer; ion implanting the first layer of polycrystalline silicon with boron containing dopant impurities; annealing the first layer of polycrystalline silicon to cause a portion of the boron dopant impurities to diffuse through the oxide layer and into the semiconductor substrate; removing the first layer of polycrystalline silicon and the first oxide layer; forming a gate insulator layer a predetermined thickness on the surface region, the predetermined thickness being substantially less than 10-15 nanometers; forming an N type polycrystalline silicon gate electrode overlying the gate insulator; and forming P type source and drain regions in the surface region aligned to the gate electrode.

Claim 13

A process for fabricating a P channel MOS transistor comprising the steps of: providing a semiconductor substrate having a surface region of N type conductivity; forming a first oxide layer having a thickness of about 10-15 nanometers overlying the surface region; forming an undoped first layer of polycrystalline silicon overlaying the first oxide layer; ion implanting the first layer of polycrystalline silicon with boron containing dopant impurities; annealing the first layer of polycrystalline silicon to cause a portion of the boron dopant impurities to diffuse through the oxide layer and into the semiconductor substrate; removing the first layer of polycrystalline silicon and the first oxide layer; forming a gate insulator layer a predetermined thickness on the surface region, the predetermined thickness being substantially less than 10-15 nanometers; forming an N type polycrystalline silicon gate electrode overlying the gate insulator; and forming P type source and drain regions in the surface region aligned to the gate electrode.

Claim 14

A process for fabricating a semiconductor device comprising the steps of: providing a semiconductor substrate having a surface; forming a diffusant penetration layer of a first predetermined thickness overlying surface; forming a diffusant source layer containing boron dopant overlaying the diffusant penetration layer; annealing the diffusant source layer to cause the boron dopant to controllably diffuse through the diffusant penetration layer and to the semiconductor substrate to form a doped region at the surface; removing the diffusant source layer and the diffusant penetration layer; forming a gate insulator of a second predetermined thickness on the surface overlying the doped region, the second predetermined thickness being substantially less than the first predetermined thickness; and forming a gate electrode doped with N type conductivity determining dopant impurities overlaying the gate insulator.

Claim 15

A process for fabricating a semiconductor device comprising the steps of: providing a semiconductor substrate having a surface; forming a diffusant penetration layer of a first predetermined thickness overlying surface; forming a diffusant source layer containing boron dopant overlaying the diffusant penetration layer; annealing the diffusant source layer to cause the boron dopant to controllably diffuse through the diffusant penetration layer and to the semiconductor substrate to form a doped region at the surface; removing the diffusant source layer and the diffusant penetration layer; forming a gate insulator of a second predetermined thickness on the surface overlying the doped region, the second predetermined thickness being substantially less than the first predetermined thickness; and forming a gate electrode doped with N type conductivity determining dopant impurities overlaying the gate insulator.

Claim 16

The process of claim 12 wherein the step of forming a diffusant source layer comprises the step of forming a layer of doped polycrystalline silicon.

Claim 17

The process of claim 13 wherein the step of forming a layer of doped polycrystalline silicon comprises the steps of: depositing a layer of undoped polycrystalline silicon; and ion implanting the undoped polycrystalline silicon with boron containing ions.

Claim 18

The process of claim 14 wherein the step of ion implanting comprises ion implanting at an energy such that the range of the boron containing ions is within the layer of undoped polycrystalline silicon.