Patent US2443613A successfully refreshed from Google Patents.
US5144571A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Direct digital synthesizer with feedback shift register
Assignee: Tektronix Inc
•
Filing: 1992-03-02
•
Granted: 1992-09-01
•
Expires: 2012-03-02
Abstract
Abstract A direct digital synthesizer (DDS) for generating an output periodic waveform from a stored digital waveform has a linear feedback shift register coonfigured as a counter. The linear feedback shift register is clocked by the internal reference clock of the DDS, and a predetermined output of the linear feedback shift register is detected to provide a control signal. The control signal causes the frequency or phase of the output waveform to be changed according to control parameters input to a control logic circuit. The control logic circuit preloads the new parameter vlaues into appropriate frequency/phase registers which are switched to the input of the accumulator in the DDS on the next cycle of the reference clock when the control signal is detected.
Inventors
- 👤 Tran Thong
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 13:15
CPC Classifications
G; G06; G06F; G06F1/00; G06F1/02; G06F1/03; G06F1/0321; G06F1/0328; G06F1/0335
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
128 words
A direct digital synthesizer for generating an output waveform from a digital waveform stored in a memory that is addressed by the output of an accumulator adding a programmable index value to the output of the accumulator for each cycle of a reference clock, the output waveform having selected frequency/phase characteristics according to the value of the programmable index value and the programmable index value being derived from one of two selectable index registers, further comprising means for generating from the reference clock a control signal for changing the programmable index value to effect a phase change for the output waveform by selecting the other index register within one cycle of the reference clock and selecting the first index register within the next cycle of the reference clock.
Claim 2
Dependent Claim
128 words
A direct digital synthesizer for generating an output waveform from a digital waveform stored in a memory that is addressed by the output of an accumulator adding a programmable index value to the output of the accumulator for each cycle of a reference clock, the output waveform having selected frequency/phase characteristics according to the value of the programmable index value and the programmable index value being derived from one of two selectable index registers, further comprising means for generating from the reference clock a control signal for changing the programmable index value to effect a phase change for the output waveform by selecting the other index register within one cycle of the reference clock and selecting the first index register within the next cycle of the reference clock.
Claim 3
Dependent Claim
73 words
A direct digital synthesizer as recited in claim 1 wherein the generating means comprises: a linear feedback shift register configured as a counter having the reference clock as an input; means for loading the linear feedback shift register with an initial count; and means for decoding the output of the linear feedback shift register to generate the control signal after a predetermined number of cycles of the reference clock from the initial count.
Claim 4
Dependent Claim
120 words
A direct digital synthesizer as recited in claim 2 wherein the linear feedback shift register comprises: a plurality of single-bit shift stages coupled in series so that the output of a prior shift stage in the series is coupled to the input of the next following shift stage in the series such that for each cycle of the reference clock the value of the prior shift stage is shifted to the next following shift stage; and a logic circuit coupled to the outputs of at least two of the shift stages to provide an input for the first shift stage in the series, the outputs of all of the shift stages forming the output of the linear feedback shift register.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-09-01 | 1996-03-02 | 1996-09-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-09-01 | 2000-03-02 | 2000-09-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-09-01 | 2004-03-02 | 2004-09-01 | $7700.00 | Window Closed / Lapsed |