US5144583A
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Dynamic semiconductor memory device with twisted bit-line structure
Assignee: Toshiba Corp
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Filing: 1990-01-04
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Granted: 1992-09-01
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Expires: 2010-01-04
Abstract
Abstract A dynamic random-access memory has bit-line pairs, word lines intersecting with the bit-line pairs, and memory cells arranged at the intersections of the bit-line pairs and the word lines, and sense amplifiers provided for the bit-line pairs, respectively. One of every two neighboring bit-line pairs is twisted at one portion, thus forming a twisted crossing section. The twisted crossing section is made of the parts of the gate electrodes of the transistors incorporated in the sense amplifier connected to the twisted bit-line pair. The bit-line pairs is twisted at a portion substantially middle with respect to the direction in which it extends, and the sensr amplifier associated with this bit-line pair is located at the twisted portion thereof.
Inventors
- 👤 Yukihito Oowaki
- 👤 Kenji Tsuchida
- 👤 Daisaburo Takashima
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 00:45
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/409; G11C11/4097; H; H10; H10B; H10B12/00; H10B12/30; H10W; H10W20/00; H10W20/40; H10W20/41; H10W20/43
Claims Analysis
Total Claims: 20
Claim 1
Independent Claim
95 words
A dynamic semiconductor memory device comprising: bit line pairs; word lines insulatively intersecting said bit lines; memory cells provided at selected ones of intersecting points between said bit lines and said word lines; sense amplifiers provide for said bit line pairs and having transistors; and at least one of two neighboring bit line pairs of said bit line pairs being twisted at at least one position thereof to have a twisted crossing section which is formed using gate electrodes of said transistors included in a sense amplifier of said at least one bit line pair.
Claim 2
Dependent Claim
95 words
A dynamic semiconductor memory device comprising: bit line pairs; word lines insulatively intersecting said bit lines; memory cells provided at selected ones of intersecting points between said bit lines and said word lines; sense amplifiers provide for said bit line pairs and having transistors; and at least one of two neighboring bit line pairs of said bit line pairs being twisted at at least one position thereof to have a twisted crossing section which is formed using gate electrodes of said transistors included in a sense amplifier of said at least one bit line pair.
Claim 3
Dependent Claim
33 words
The device according to claim 1, wherein said at least one bit line pair is twisted at a substantially center position along a longitudinal direction thereof, in which said sense amplifier is provided.
Claim 4
Dependent Claim
46 words
The device according to claim 1, wherein said at least one bit line pair is twisted at a substantially center position along a longitudinal direction thereof, and is located between two bit lines of the other bit line pair of said two neighboring bit line pair.
Claim 5
Dependent Claim
54 words
The device according to claim 1, wherein said at least one bit line pair is twisted at a substantially center position along a longitudinal direction thereof, and wherein the other bit line pair of said two neighboring bit line pair is located between two bit lines of said at least one bit line pair.
Claim 6
Dependent Claim
52 words
The device according to claim 1, wherein one of said two neighboring bit line pairs has one of two bit lines of the other of said two neighboring bit line pairs located therebetween, and wherein the other bit line pair is twisted at a substantially center position along a longitudinal direction thereof.
Claim 7
Dependent Claim
125 words
A dynamic random access memory comprising: folded type parallel bit line pairs; word lines insulatively intersecting said bit lines; memory cells provided at selected ones of intersecting points between said bit lines and said word lines; sense amplifiers provided for said bit line pairs and having transistors; and every two neighboring bit line pairs of said bit line pairs having a twisted bit line pair which is twisted at a single selected position in a substantially central region along the longitudinal direction thereof to provide a twisted crossing section, and a straight bit line pair having two straight bit lines, one pair of said twisted bit line pair and said straight bit line pair being located between two bit lines of the other pair thereof.
Claim 8
Dependent Claim
125 words
A dynamic random access memory comprising: folded type parallel bit line pairs; word lines insulatively intersecting said bit lines; memory cells provided at selected ones of intersecting points between said bit lines and said word lines; sense amplifiers provided for said bit line pairs and having transistors; and every two neighboring bit line pairs of said bit line pairs having a twisted bit line pair which is twisted at a single selected position in a substantially central region along the longitudinal direction thereof to provide a twisted crossing section, and a straight bit line pair having two straight bit lines, one pair of said twisted bit line pair and said straight bit line pair being located between two bit lines of the other pair thereof.
Claim 9
Dependent Claim
134 words
A dynamic random access memory comprising: folded type parallel bit line pairs; word lines insulatively intersecting said bit line pairs; memory cells provided at selected ones of intersecting points between said bit lines and said word lines; sense amplifiers provided for said bit line pairs and having transistors; and every two neighboring bit line pairs of said bit line pairs having a twisted bit line pair which is twisted at a selected position in a middle region along the longitudinal direction thereof to provide a twisted crossing section; wherein said sense amplifiers include a certain sense amplifier circuit for said twisted bit line pair, said certain sense amplifier circuit having metal-oxide-semiconductor field effect transistors some of which are used as at least one part of a contact region for forming said twisted crossing section.
Claim 10
Dependent Claim
134 words
A dynamic random access memory comprising: folded type parallel bit line pairs; word lines insulatively intersecting said bit line pairs; memory cells provided at selected ones of intersecting points between said bit lines and said word lines; sense amplifiers provided for said bit line pairs and having transistors; and every two neighboring bit line pairs of said bit line pairs having a twisted bit line pair which is twisted at a selected position in a middle region along the longitudinal direction thereof to provide a twisted crossing section; wherein said sense amplifiers include a certain sense amplifier circuit for said twisted bit line pair, said certain sense amplifier circuit having metal-oxide-semiconductor field effect transistors some of which are used as at least one part of a contact region for forming said twisted crossing section.
Claim 11
Dependent Claim
24 words
The memory according to claim 6, wherein said twisted bit line pair has two bit lines which surround a bit line pair neighboring thereto.
Claim 12
Dependent Claim
30 words
The memory according to claim 6, wherein said twisted bit line pair is surrounded by two bit lines of a bit line pair neighboring to said twisted bit line pair.
Claim 13
Dependent Claim
30 words
The memory according to claim 6, wherein said twisted bit line pair surrounds one of two bit lines of a bit line pair neighboring to said twisted bit line pair.
Claim 14
Dependent Claim
103 words
A dynamic random access memory comprising: folded type parallel bit line pairs; word lines insulatively intersecting said bit line pairs; memory cells provided at selected ones of intersecting points between said bit lines and said word lines; and sense amplifiers provided for said bit line pairs and having transistors; every set of three neighboring bit line pairs of said bit line pairs overlapping one another in such a manner that each bit line pair of said three neighboring bit line pairs has two bit lines located therebetween respectively selected from the remaining two bit line pairs of said three neighboring bit line pairs.
Claim 15
Dependent Claim
103 words
A dynamic random access memory comprising: folded type parallel bit line pairs; word lines insulatively intersecting said bit line pairs; memory cells provided at selected ones of intersecting points between said bit lines and said word lines; and sense amplifiers provided for said bit line pairs and having transistors; every set of three neighboring bit line pairs of said bit line pairs overlapping one another in such a manner that each bit line pair of said three neighboring bit line pairs has two bit lines located therebetween respectively selected from the remaining two bit line pairs of said three neighboring bit line pairs.
Claim 16
Dependent Claim
121 words
The device according to claim 11, wherein said memory cells comprise: a first array of memory cells, associated with a first word line, located at alternating ones of intersecting points defined between said first word line and the bit lines of said every three neighboring bit line pairs; and a second array of memory cells, associated with a second word line disposed adjacent to said first word line, located at alternating ones of intersecting points defined between said second word line and the bit lines of said every three neighboring bit line pairs, said first and second array of memory cells being staggered such that memory cells are located at alternating intersecting points of said word lines with each bit line.
Claim 17
Dependent Claim
50 words
The memory according to claim 12, wherein said bit line pairs include a set of three neighboring bit line pairs which include at least two twisted bit line pairs one of which is twisted at a substantially central position along a longitudinal direction thereof to provide a twisted crossing section.
Claim 18
Dependent Claim
42 words
The memory according to claim 13, wherein the other of said two twisted bit line pairs is twisted at selected positions along the longitudinal direction thereof which are different from said central position, thereby to provide a plurality of twisted crossing sections.
Claim 19
Dependent Claim
141 words
A dynamic random access memory comprising: folded type parallel bit line pairs; word lines insulatively crossing said bit lines, said word line including a first word line and a second word line adjacent to said first word line; memory cells provided at selected ones of intersecting points between said bit lines and said word lines; sense amplifiers provided for said bit line pairs and having transistors; and two neighboring bit line pairs of said bit line pairs having a first pair of bit lines which is twisted at a single selected position thereof to have a twisted crossing section, and a second pair of bit lines which are straight lines and one of which is located between said first pair of bit lines, said first pair of bit lines being twisted at a substantially central position along the longitudinal direction thereof.
Claim 20
Dependent Claim
141 words
A dynamic random access memory comprising: folded type parallel bit line pairs; word lines insulatively crossing said bit lines, said word line including a first word line and a second word line adjacent to said first word line; memory cells provided at selected ones of intersecting points between said bit lines and said word lines; sense amplifiers provided for said bit line pairs and having transistors; and two neighboring bit line pairs of said bit line pairs having a first pair of bit lines which is twisted at a single selected position thereof to have a twisted crossing section, and a second pair of bit lines which are straight lines and one of which is located between said first pair of bit lines, said first pair of bit lines being twisted at a substantially central position along the longitudinal direction thereof.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-09-01 | 1996-03-02 | 1996-09-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-09-01 | 2000-03-02 | 2000-09-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-09-01 | 2004-03-02 | 2004-09-01 | $7700.00 | Window Closed / Lapsed |