Method and apparatus for sharing information between a plurality of processing units

Claim 1

A data processing system, comprising: a data bus; and a plurality of nodes connected to the data bus, at least one of said plurality of nodes comprises: processor means for generating a data signal, an address signal and a memory write signal; a dual port memory unit having a first storage area for storing data local to a respective node and a second storage area for storing data shared between the plurality of nodes; a local bus connecting the processor means to a first port of the memory unit; and write sensing means connected to the data bus and also to the processing unit through the local bus, said write sensing means comprising: first comparator means for comparing address signals sensed from the local bus with a first predetermined value; second comparator means for comparing the address signals sensed from the local bus with a second predetermined value; first latch means for holding the data signals, address signals and write signals; first offset logic means for normalizing the address signal in response to the address signal being released from the first latch means; first request FIFO means for receiving data signals, and write signals from the first latch means, in response to receipt of a signal by the first latch means indicating that the address signal is of a value larger the first predetermined value, of a value smaller than the second predetermined value, and address signals from the first offset logic means; transmitter means for transmitting the sensed data signals, normalized address signals and memory write signals in order of receipt by the first request FIFO means; third comparator means for comparing address signals sensed from the data bus with a third predetermined value; fourth comparator means for comparing the address signals sensed from the data bus with a fourth predetermined value; and second offset logic means for offsetting the address signal to its original value upon a determination that the address signal is of a value larger than the third predetermined value and of a value smaller than the fourth predetermined value; the at least one of the processing nodes further comprising read sensing means connected between the write sensing means and a second port of the memory, unit, said read sensing means comprising: correction logic means for generating corrected signals for data sensed from the data bus by the write sensing means; second request FIFO means for receiving data signals, address signals and write sense signals from the write sense logic; and combining means for combining the correction signals with the data signals producing a corrected data signal to be delivered to the shared storage area of the memory unit.