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US5155822A Expired / Lapsed US ⏱️ 0.0 years remaining

High performance graphics workstation

Assignee: Hewlett Packard Development Co LP
•
Filing: 1987-08-13
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Granted: 1992-10-13
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Expires: 2007-08-13
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Abstract

Abstract A stand-alone graphics workstation including a digital computer host and a graphics processing subsystem is disclosed. Address data relating to the graphics subsystem components is mapped into the host system virtual memory. The application processes residing in the host are thereby able to communicate directly with the graphics subsystem components, as, e.g. the structure memory, without the need of a direct memory access hardware arrangement or device drivers.

Inventors

  • 👤 Peter L. Doyle
  • 👤 John P. Ellenberger
  • 👤 Ellis O. Jones
  • 👤 David C. Carver
  • 👤 Steven D. DiPirro
  • 👤 Branko J. Gerovac
  • 👤 William P. Armstrong
  • 👤 Ellen S. Gibson
  • 👤 Raymond E. Shapiro
  • 👤 Kevin C. Rutherford
  • 👤 William C. Roach

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-09 13:47
CPC Classifications
G; G06; G06T; G06T17/00

Claims Analysis

Total Claims: 6
Claim 1
Independent Claim 253 words
A method of operating a computer system comprising a first central processing unit providing a plurality of process virtual address spaces and a system virtual address space, a primary bus having a reserved I/O address space with a starting and ending address, a control processor having mapping registers, the control processor coupled by the primary bus to the first central processing unit, and local memory connected to the local control processor by a local bus, comprising the steps of: a) operating the first central processing unit to transfer the starting and ending addresses of the reserved I/O space to the mapping registers; b) operating the first central processing unit to relocate the local memory to be within the starting and ending addresses of the reserved I/O space; c) operating the first central processing unit to map the local memory of the control processor into the system virtual address space; d) operating the first central processing unit to provide a separate one or more of the process virtual address spaces to each of a plurality of processes; e) operating the first central processing unit to enable the plurality of processes to access the portion of the system virtual address space to which the local memory is mapped such that each of the plurality of processes addresses the local memory by directly addressing the system virtual address space in which the local memory is mapped; and f) one or more of the plurality of processes writing data representative of displayable graphics to the local memory.
Claim 2
Independent Claim 253 words
A method of operating a computer system comprising a first central processing unit providing a plurality of process virtual address spaces and a system virtual address space, a primary bus having a reserved I/O address space with a starting and ending address, a control processor having mapping registers, the control processor coupled by the primary bus to the first central processing unit, and local memory connected to the local control processor by a local bus, comprising the steps of: a) operating the first central processing unit to transfer the starting and ending addresses of the reserved I/O space to the mapping registers; b) operating the first central processing unit to relocate the local memory to be within the starting and ending addresses of the reserved I/O space; c) operating the first central processing unit to map the local memory of the control processor into the system virtual address space; d) operating the first central processing unit to provide a separate one or more of the process virtual address spaces to each of a plurality of processes; e) operating the first central processing unit to enable the plurality of processes to access the portion of the system virtual address space to which the local memory is mapped such that each of the plurality of processes addresses the local memory by directly addressing the system virtual address space in which the local memory is mapped; and f) one or more of the plurality of processes writing data representative of displayable graphics to the local memory.
Claim 3
Dependent Claim 21 words
The method according to claim 1, further comprising the step of preventing the plurality of processes from directly referencing physical addresses.
Claim 4
Dependent Claim 97 words
A computer system which comprises: a first central processing unit having a plurality of process virtual address spaces and a system virtual address space; a control processor; local memory, contained within a computer graphics subsystem; a local bus coupling the control processor to the local memory; a primary bus coupling the first central processing unit to the control processor; a reserved I/O address space having starting and ending addresses on the primary bus; and mapping registers associated with the at least one local control processor for storing the starting and ending addresses of the reserved I/O space.
Claim 5
Dependent Claim 97 words
A computer system which comprises: a first central processing unit having a plurality of process virtual address spaces and a system virtual address space; a control processor; local memory, contained within a computer graphics subsystem; a local bus coupling the control processor to the local memory; a primary bus coupling the first central processing unit to the control processor; a reserved I/O address space having starting and ending addresses on the primary bus; and mapping registers associated with the at least one local control processor for storing the starting and ending addresses of the reserved I/O space.
Claim 6
Dependent Claim 20 words
The computer system according to claim 3, wherein the first central processing unit prevents processes from directly referencing physical addresses.

References Cited (Backward Citations)

US4453211A Cited
US4815010A Cited
US4777589A Cited
US4769636A Cited
US4742447A Cited
US4802085A Cited
US4956771A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1995-10-13 1996-04-13 1996-10-13 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1999-10-13 2000-04-13 2000-10-13 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2003-10-13 2004-04-13 2004-10-13 $7700.00 Window Closed / Lapsed

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