Fabricating a memory cell with an improved capacitor

Claim 1

A process for producing a dynamic random access memory cell having a merged stacked trench and stacked capacitor comprising the steps of: (a) selectively forming field oxide areas on the surface of a semiconductor substrate while leaving device areas for fabrication of field effect devices, (b) forming trenches in said device areas adjacent the edges of said field oxide areas, (c) forming a first insulating layer on the surface of said trenches, (d) depositing a first layer of polysilicon on the surface of said substrate, including the sidewalls and bottom of said trench, of a thickness to substantially fill said trench, (e) removing portions of said first polysilicon layer but leaving portions thereof for the gate structure in said device area, portions over said field oxide, and portions in said trench, (f) forming source and drain regions in said device areas by masking and ion implantation techniques, utilizing said portions of said first polysilicon layer, for gate structure as a blocking mask, (g) depositing a second insulating layer of silicon oxide over said substrate and forming openings over as said source regions, and subsequently removing said portions of said first polysilicon layer in said trench. (h) forming a second doped polysilicon layer over the surface of said substrate including the sidewalls and bottom of said trench and opening over said source region, said second polysilicon layer to serve as a first capacitor plate, (i) forming a third insulating layer over the surface of said second polysilicon layer, (j) forming a third doped polysilicon layer over said insulating layer, said third polysilicon layer to serve as a second capacitor plate, said resultant structure forming a memory cell with a coupled capacitor and a field effect transistor.