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US5158899A Expired / Lapsed US ⏱️ 0.0 years remaining

Method of manufacturing input circuit of semiconductor device

Assignee: Mitsubishi Electric Corp
•
Filing: 1991-05-06
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Granted: 1992-10-27
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Expires: 2011-05-06
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Abstract

Abstract A method of manufacturing an input circuit of a semiconductor device comprises the steps of forming an N well on the main surface of a P type semiconductor substrate, forming a P well by injecting P type ions upwardly from the N well, and forming an N type region by injecting ions onto the main surface of the P well. An input voltage is applied to the N type region, and the input voltage is applied to the internal circuit formed on the main surface of the semiconductor substrate. A P-N junction is formed between the P well and an N type diffusion layer. When the P-N junction conducts due to the application of an excess voltage into the input voltage, current caused by the excess voltage is absorbed through the N type region formed on the main surface of the N well.

Inventors

  • 👤 Tadato Yamagata

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-08 23:04
CPC Classifications
H; H10; H10D; H10D89/00; H10D89/60; H10D89/601

Claims Analysis

Total Claims: 13
Claim 1
Independent Claim 200 words
A method of manufacturing an input circuit of a semiconductor device on a surface of a semiconductor substrate of a first conductivity type, comprising the steps of: on a main surface of the semiconductor substrate, forming a first region of a second conductivity type opposite to said first conductivity type having a main surface, forming an impurity region of the first conductivity type in said first region of the second conductivity type and on said main surface, and a second region of the second conductivity type in said impurity region of the first conductivity type for applying an input voltage, and forming a third region of said second conductivity type kept at a prescribed potential on the main surface of said first region of the second conductivity type, said input voltage being applied to the internal circuit formed on the main surface of said semiconductor substrate, a P-N junction being formed between said impurity region of the first conductivity type and said second region of the second conductivity type, an excess voltage being applied to said input voltage thereby absorbing current caused by said excess voltage through the third region of said second conductivity type when said P-N junction conducts.
Claim 2
Independent Claim 200 words
A method of manufacturing an input circuit of a semiconductor device on a surface of a semiconductor substrate of a first conductivity type, comprising the steps of: on a main surface of the semiconductor substrate, forming a first region of a second conductivity type opposite to said first conductivity type having a main surface, forming an impurity region of the first conductivity type in said first region of the second conductivity type and on said main surface, and a second region of the second conductivity type in said impurity region of the first conductivity type for applying an input voltage, and forming a third region of said second conductivity type kept at a prescribed potential on the main surface of said first region of the second conductivity type, said input voltage being applied to the internal circuit formed on the main surface of said semiconductor substrate, a P-N junction being formed between said impurity region of the first conductivity type and said second region of the second conductivity type, an excess voltage being applied to said input voltage thereby absorbing current caused by said excess voltage through the third region of said second conductivity type when said P-N junction conducts.
Claim 3
Dependent Claim 50 words
The method of manufacturing the input circuit of the semiconductor device according to claim 1, further comprising forming of a fourth region of the second conductivity type adjacent to said second region of the second conductivity type on the main surface of said impurity region of the first conductivity type.
Claim 4
Dependent Claim 29 words
The manufacturing method according to claim 1, wherein said step of forming the first impurity region of the second conductivity type comprises the step of forming by injecting ions.
Claim 5
Dependent Claim 28 words
The manufacturing method according to claim 3, wherein said step of forming the impurity region of the first conductivity type comprises the step of forming by injecting ions.
Claim 6
Dependent Claim 28 words
The manufacturing method according to claim 4, wherein said step of forming the second region of the second conductivity type comprises the step of forming by injecting ions.
Claim 7
Dependent Claim 28 words
The manufacturing method according to claim 2, wherein said step of forming the fourth region of the second conductivity type comprises the step of forming by injecting ions.
Claim 8
Independent Claim 196 words
A method of manufacturing an input circuit of a semiconductor device on a semiconductor substrate having a first conductivity type, comprising the steps of; on a main surface of the semiconductor substrate forming a first region of a second conductivity type opposite to said first conductivity type, injecting ions to form an impurity region of the first conductivity type in said first region of the second conductivity type and on said main surface, forming a second region of the second conductivity type in said impurity region of the first conductivity type for applying an input voltage, and forming a third region of the second conductivity type kept at a prescribed potential on the main surface of said first region of the second conductivity type, said input voltage being applied to the internal circuit formed on the main surface of said semiconductor substrate, a P-N junction being formed between said impurity region of the first conductivity type and said second region of the second conductivity type, an excess voltage being applied to said input voltage thereby absorbing current caused by said excess voltage through the third region of said second conductivity type when said P-N junction conducts.
Claim 9
Independent Claim 196 words
A method of manufacturing an input circuit of a semiconductor device on a semiconductor substrate having a first conductivity type, comprising the steps of; on a main surface of the semiconductor substrate forming a first region of a second conductivity type opposite to said first conductivity type, injecting ions to form an impurity region of the first conductivity type in said first region of the second conductivity type and on said main surface, forming a second region of the second conductivity type in said impurity region of the first conductivity type for applying an input voltage, and forming a third region of the second conductivity type kept at a prescribed potential on the main surface of said first region of the second conductivity type, said input voltage being applied to the internal circuit formed on the main surface of said semiconductor substrate, a P-N junction being formed between said impurity region of the first conductivity type and said second region of the second conductivity type, an excess voltage being applied to said input voltage thereby absorbing current caused by said excess voltage through the third region of said second conductivity type when said P-N junction conducts.
Claim 10
Dependent Claim 50 words
The method of manufacturing the input circuit of the semiconductor device according to claim 7, further comprising forming of a fourth region of the second conductivity type adjacent to said second region of the second conductivity type on the main surface of said impurity region of the first conductivity type.
Claim 11
Dependent Claim 28 words
The manufacturing method according to claim 8, wherein said step of forming the fourth region of the second conductivity type comprises the step of forming by injecting ions.
Claim 12
Independent Claim 212 words
A method, free of requirement for growth of epitaxial layers, of manufacturing on a surface of a semiconductor substrate of a first conductivity type an input circuit of a semiconductor device, comprising the steps of: on a main surface of the semiconductor substrate, forming by ion injection a first region of a second conductivity type opposite to said first conductivity type and having a main surface, forming an impurity region of the first conductivity type in said first region of the second conductivity type and on said main surface, and a second region of the second conductivity type in said impurity region of the first conductivity type for applying an input voltage, and forming a third region of the second conductivity type kept at a prescribed potential on the main surface of said first region of the second conductivity type, said input voltage being applied to the internal circuit formed on the main surface of said semiconductor substrate, a P-N junction being formed between said impurity region of the first conductivity type and said second region of the second conductivity type, an excess voltage being applied to said input voltage thereby absorbing current caused by said excess voltage through the third region of said second conductivity type when said P-N junction conducts.
Claim 13
Independent Claim 212 words
A method, free of requirement for growth of epitaxial layers, of manufacturing on a surface of a semiconductor substrate of a first conductivity type an input circuit of a semiconductor device, comprising the steps of: on a main surface of the semiconductor substrate, forming by ion injection a first region of a second conductivity type opposite to said first conductivity type and having a main surface, forming an impurity region of the first conductivity type in said first region of the second conductivity type and on said main surface, and a second region of the second conductivity type in said impurity region of the first conductivity type for applying an input voltage, and forming a third region of the second conductivity type kept at a prescribed potential on the main surface of said first region of the second conductivity type, said input voltage being applied to the internal circuit formed on the main surface of said semiconductor substrate, a P-N junction being formed between said impurity region of the first conductivity type and said second region of the second conductivity type, an excess voltage being applied to said input voltage thereby absorbing current caused by said excess voltage through the third region of said second conductivity type when said P-N junction conducts.

References Cited (Backward Citations)

US3212162A Cited
JPS58165369A Cited
JPS6048906A Cited
US4692781A Cited
US4692781B1 Cited
US4692781B2 Cited
US4795716A Cited
JPS648796A Cited
US4983534A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1995-10-27 1996-04-27 1996-10-27 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1999-10-27 2000-04-27 2000-10-27 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2003-10-27 2004-04-27 2004-10-27 $7700.00 Window Closed / Lapsed

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