US5162260A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Stacked solid via formation in integrated circuit systems
Assignee: HP Inc
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Filing: 1991-01-07
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Granted: 1992-11-10
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Expires: 2011-01-07
Abstract
Abstract A method of forming solid copper vias in a dielectric layer permits stacked vias in a multi-chip carrier. A dielectric layer is deposited over a substrate and lines of a first interconnect layer formed on the substrate. An aperture formed in the dielectric layer is filled with copper by deposition to form a hollow via. Using a photoresist mask, the hollow via is filled solid by electroplating a second amount of copper. The photoresist is then stripped and excess copper extending from the via is polished flat. A second interconnect layer can be formed on the resulting structure. The foregoing steps can be iterated to build a multi-layer structure with stacked vias.
Inventors
- 👤 Jacques Leibovitz
- 👤 Maria L. Cobarruviaz
- 👤 Kenneth D. Scholz
- 👤 Clinton C. Chao
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 02:31
CPC Classifications
H; H05; H05K; H05K3/00; H05K3/40; H05K3/42; H05K3/421; H05K3/46; H05K3/4644; H05K3/4647; H10; H10W; H10W20/00; H10W20/40; H10W20/41; H10W20/42; H05K2201/00; H05K2201/01; H05K2201/0137; H05K2201/0154; H05K2201/09; H05K2201/09209; H05K2201/095; H05K2201/09563; H05K2203/00; H05K2203/05; H05K2203/0502; H05K2203/0542; H05K2203/07; H05K2203/0703; H05K2203/0733; H05K3/0011; H05K3/0017; H05K3/0041; H05K3/22; H05K3/24; H05K3/243; H05K3/38; H05K3/388; H05K3/423; H05K3/425; H05K3/426; H05K3/467
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
143 words
A method of forming an integrated circuit structure including solid vias, said method comprising the sequential steps of; a) forming a first circuit pattern on a substrate; b) depositing a first dielectric layer; c) defining apertures in said first dielectric layer; d) depositing a first metallization layer so as to form an upper conductive layer including a plurality of first dielectric layer vias through said apertures, said first dielectric layers being initially hollow, said first metallization layer consisting of a metal conductive layer sandwiched between metal adhesive layers which facilitate bonding to adjacent dielectric layer vias; e) depositing a photoresist layer on the structure resulting from step d) and defining apertures in said photoresist layer; f) filing said first dielectric layer vias with solid material so that said first dielectric layer vias become solid; and g) removing the remainder of said photoresist layer.
Claim 2
Independent Claim
143 words
A method of forming an integrated circuit structure including solid vias, said method comprising the sequential steps of; a) forming a first circuit pattern on a substrate; b) depositing a first dielectric layer; c) defining apertures in said first dielectric layer; d) depositing a first metallization layer so as to form an upper conductive layer including a plurality of first dielectric layer vias through said apertures, said first dielectric layers being initially hollow, said first metallization layer consisting of a metal conductive layer sandwiched between metal adhesive layers which facilitate bonding to adjacent dielectric layer vias; e) depositing a photoresist layer on the structure resulting from step d) and defining apertures in said photoresist layer; f) filing said first dielectric layer vias with solid material so that said first dielectric layer vias become solid; and g) removing the remainder of said photoresist layer.
Claim 3
Dependent Claim
13 words
A method as recited in claim 1 wherein said metal conductive layer copper.
Claim 4
Dependent Claim
49 words
A method as recited in claim 2, further comprising forming a second circuit pattern including second circuit layer lines on the structure resulting from step g so that at least one of said second circuit layer lines is stacked on a respective one of said first dielectric layer vias.
Claim 5
Dependent Claim
60 words
A method as recited in claim 3 further comprising a second iteration of steps b through g to form a plurality of second dielectric layer vias over said second circuit pattern so that at least one of said second dielectric layer vias is stacked on a respective one of said first dielectric layer vias to form a multiple layer interconnect.
Claim 6
Independent Claim
174 words
A method of forming an integrated circuit structure including solid vias, said method comprising the sequential steps of: a) forming a first circuit pattern on a substrate; b) depositing a first dielectric layer; c) defining apertures in said first dielectric layer; d) depositing a first metallization layer so as to form an upper conductive layer including a plurality of first dielectric layer vias through said apertures, said vias being initially hollow, said first metallization layer including a metal conductive layer sandwiched between metal adhesive layer; e) depositing a photoresist layer on the structure resulting from step d) and defining apertures in said photoresist layer; f) filling said first dielectric layer vias with conductive material so that said first dielectric layer vias become solid; g) polishing the structure resulting from step f so as to remove excess solid conductive material so that a composite conductive layer with a planar top surface and integral solid vias remains; and h) photolithographically patterning said composite conductive layer so as to define a first upper layer of conductive traces.
Claim 7
Independent Claim
174 words
A method of forming an integrated circuit structure including solid vias, said method comprising the sequential steps of: a) forming a first circuit pattern on a substrate; b) depositing a first dielectric layer; c) defining apertures in said first dielectric layer; d) depositing a first metallization layer so as to form an upper conductive layer including a plurality of first dielectric layer vias through said apertures, said vias being initially hollow, said first metallization layer including a metal conductive layer sandwiched between metal adhesive layer; e) depositing a photoresist layer on the structure resulting from step d) and defining apertures in said photoresist layer; f) filling said first dielectric layer vias with conductive material so that said first dielectric layer vias become solid; g) polishing the structure resulting from step f so as to remove excess solid conductive material so that a composite conductive layer with a planar top surface and integral solid vias remains; and h) photolithographically patterning said composite conductive layer so as to define a first upper layer of conductive traces.
Claim 8
Dependent Claim
60 words
A method as recited in claim 5 further comprising a second iteration of steps b through h to form a plurality of second dielectric layer vias over said second circuit pattern so that at least one of said second dielectric layer vias is stacked on a respective one of said first dielectric layer vias to form a multiple layer interconnect.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-11-10 | 1996-05-11 | 1996-11-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-11-10 | 2000-05-11 | 2000-11-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-11-10 | 2004-05-11 | 2004-11-10 | $7700.00 | Window Closed / Lapsed |