Coding and decoding apparatus of variable length data

Claim 1

An apparatus for encoding data words of variable bit length supplied at a first data rate into data words of constant bit length supplied at a second data rate, comprising: first register means for receiving a data word of variable bit length of up to m bits at said first data rate; shifter means for bit shifting said data word of variable bit length from said first register means in accordance with a control signal, thereby forming a first shifted data word and a second shifted data word; control signal generating means for generating said control signal in accordance with a number of bits of previously shifted data words awaiting output; concatenating means for concatenating said first shifted data word and said bits of previously shifted data words awaiting output, thereby forming a concatenated data word; second register means for storing said concatenated data word, said concatenated data word being said bits of previously shifted data awaiting output with respect to a next data word of variable bit length when said concatenated data word has less than n bits; third register means for storing said second shifted data word, said second shifted data word being said bits of previously shifted data awaiting output with respect to a next data word of variable bit length when said concatenated data word has n bits; zero value data generating means for generating zero value data for clearing said third register means when said second shifted data word is concatenated with a next first shifted data word; buffering means for receiving said concatenated data word from said second register means when said concatenated data word has n bits and for storing said concatenated data word as one of a plurality of data words of constant bit length; and output means for outputting said data words of constant bit length from said buffering means at said second data rate.

Claim 2

An apparatus for encoding data words of variable bit length supplied at a first data rate into data words of constant bit length supplied at a second data rate, comprising: first register means for receiving a data word of variable bit length of up to m bits at said first data rate; shifter means for bit shifting said data word of variable bit length from said first register means in accordance with a control signal, thereby forming a first shifted data word and a second shifted data word; control signal generating means for generating said control signal in accordance with a number of bits of previously shifted data words awaiting output; concatenating means for concatenating said first shifted data word and said bits of previously shifted data words awaiting output, thereby forming a concatenated data word; second register means for storing said concatenated data word, said concatenated data word being said bits of previously shifted data awaiting output with respect to a next data word of variable bit length when said concatenated data word has less than n bits; third register means for storing said second shifted data word, said second shifted data word being said bits of previously shifted data awaiting output with respect to a next data word of variable bit length when said concatenated data word has n bits; zero value data generating means for generating zero value data for clearing said third register means when said second shifted data word is concatenated with a next first shifted data word; buffering means for receiving said concatenated data word from said second register means when said concatenated data word has n bits and for storing said concatenated data word as one of a plurality of data words of constant bit length; and output means for outputting said data words of constant bit length from said buffering means at said second data rate.

Claim 3

An apparatus for decoding data words of constant bit length into data words of variable bit length, comprising: shifter means for shifting a data word of constant bit length by a number of bits in accordance with a control signal, thereby forming a shifted data word; control signal generating means for generating said control signal in accordance with a number of bits of a previously output data word of variable bit length; concatenating means for concatenating said shifted data word and bits of previously shifted data words awaiting decoding, thereby forming a concatenated data word; and determining means supplied with m bits of said concatenated data word for determining which of said m bits correspond to a data word of variable bit length, and for outputting said data word of variable bit length and the number of bits of said data word of variable bit length.

Claim 4

An apparatus for decoding data words of constant bit length into data words of variable bit length, comprising: shifter means for shifting a data word of constant bit length by a number of bits in accordance with a control signal, thereby forming a shifted data word; control signal generating means for generating said control signal in accordance with a number of bits of a previously output data word of variable bit length; concatenating means for concatenating said shifted data word and bits of previously shifted data words awaiting decoding, thereby forming a concatenated data word; and determining means supplied with m bits of said concatenated data word for determining which of said m bits correspond to a data word of variable bit length, and for outputting said data word of variable bit length and the number of bits of said data word of variable bit length.