US5166955A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Signal detection apparatus for detecting digital information from a PCM signal
Assignee: Panasonic Holdings Corp
•
Filing: 1990-11-26
•
Granted: 1992-11-24
•
Expires: 2010-11-26
Abstract
Abstract A signal detection apparatus detects digital information contained in a binary baseband PCM signal transmitted on a communication transmission channel or recorded on a recording medium. A first equalizer equalizes the PCM signal to reduce intersymbol interference. A clock reproducer reproduces a clock signal synchronized with the timing of the digital information using an output signal of the first equalizer. A second equalizer subjects the output signal of the first equalizer to partial response equalization. A decoding circuit decodes the digital information from an output signal of the second equalizer at a timing of the clock signal. A stable clock signal is easily reproduced and the digital information is detected at a lower bit error rate.
Inventors
- 👤 Haruo Ohta
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 03:07
CPC Classifications
G; G11; G11B; G11B20/00; G11B20/10; G11B20/18; G11B20/1806; G11B20/1813; G11B20/10009; H; H04; H04L; H04L25/00; H04L25/38; H04L25/40; H04L25/49; H04L25/497
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
142 words
A signal detection apparatus for detecting digital information from a PCM signal, comprising: a first equalization means for equalizing a binary baseband PCM signal transmitted through a transmission channel or reproduced from a recording medium to reduce the intersymbol interference; a clock reproducing means for reproducing a clock signal from an output signal of said first equalization means, said clock reproducing means comprising a phase locked loop circuit having a phase comparator for comparing a phase of the output signal of said first equalization means at a zero-cross point thereof with a reference clock phase; a second equalization means for subjecting the output signal of said first equalization means to partial response equalization; and a decoding means for decoding digital information from an output signal of said second equalization means in response to the clock signal reproduced by said clock reproducing means.
Claim 2
Dependent Claim
142 words
A signal detection apparatus for detecting digital information from a PCM signal, comprising: a first equalization means for equalizing a binary baseband PCM signal transmitted through a transmission channel or reproduced from a recording medium to reduce the intersymbol interference; a clock reproducing means for reproducing a clock signal from an output signal of said first equalization means, said clock reproducing means comprising a phase locked loop circuit having a phase comparator for comparing a phase of the output signal of said first equalization means at a zero-cross point thereof with a reference clock phase; a second equalization means for subjecting the output signal of said first equalization means to partial response equalization; and a decoding means for decoding digital information from an output signal of said second equalization means in response to the clock signal reproduced by said clock reproducing means.
Claim 3
Dependent Claim
147 words
A signal detection apparatus for detecting digital information from a PCM signal, comprising: a first equalization means for equalizing a binary baseband PCM signal transmitted through a transmission channel or reproduced from a recording medium; a clock means for reproducing a clock signal from an output signal of said first equalization means, said clock reproducing means comprising a phase locked loop circuit having a phase comparator for comparing a phase of the output signal of said first equalization means at a zero-cross point thereof with a reference clock phase; an analog-to-digital conversion means for sampling and quantizing the output signal of said first equalization means in response to said clock signal; a digital equalization means for subjecting a digital output signal of said analog-to-digital conversion means to partial response equalization; and a decoding means for decoding digital information from an output signal of said digital equalization means.
Claim 4
Dependent Claim
147 words
A signal detection apparatus for detecting digital information from a PCM signal, comprising: a first equalization means for equalizing a binary baseband PCM signal transmitted through a transmission channel or reproduced from a recording medium; a clock means for reproducing a clock signal from an output signal of said first equalization means, said clock reproducing means comprising a phase locked loop circuit having a phase comparator for comparing a phase of the output signal of said first equalization means at a zero-cross point thereof with a reference clock phase; an analog-to-digital conversion means for sampling and quantizing the output signal of said first equalization means in response to said clock signal; a digital equalization means for subjecting a digital output signal of said analog-to-digital conversion means to partial response equalization; and a decoding means for decoding digital information from an output signal of said digital equalization means.
Claim 5
Dependent Claim
16 words
A signal detection apparatus according to claim 2, wherein said decoding means comprises a Viterbi decoder.
References Cited (Backward Citations)
US3760111A
Cited
US3872381A
Cited
US4123625A
Cited
US4247940A
Cited
US4433424A
Cited
US4580176A
Cited
US4775984A
Cited
US4847871A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-11-24 | 1996-05-25 | 1996-11-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-11-24 | 2000-05-25 | 2000-11-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-11-24 | 2004-05-25 | 2004-11-24 | $7700.00 | Window Closed / Lapsed |