Semiconductor integrated circuit

Claim 2

A semiconductor integrated circuit comprising: a dielectric substrate having opposed front and rear surfaces; a field effect transistor disposed on the front surface of said dielectric substrate having a source, a gate, and a drain, said gate having an impedance; a rear surface electrode disposed on the rear surface of said dielectric substrate; a gate bias bonding pad disposed on the front surface of said dielectric substrate and electrically connected to said gate for applying a bias to said gate of said field effect transistor; a current path electrically connecting said gate bias bonding pad and said gate and having substantially the same impedance as said gate; an electrically conducting via-hole extending through said dielectric substrate connecting one of the source and drain of said field effect transistor with said rear surface electrode; and an auxiliary current path electrically connecting said current path with said rear surface electrode, said auxiliary current path comprising a high resistance material not altering the impedance of said the gate.

Claim 3

A semiconductor integrated circuit as defined in claim 1 comprising: a semiconductor layer disposed on the front surface of said dielectric substrate; and an active layer disposed in said semiconductor layer wherein said source and drain are disposed on said active layer and said gate is disposed between said source and said drain.

Claim 4

A semiconductor integrated circuit as defined in claim 1 wherein said via-hole is disposed directly opposite one of said source and said drain.

Claim 5

A semiconductor integrated circuit as defined in claim 1 including a capacitor connected to said gate bias bonding pad.

Claim 6

A semiconductor integrated circuit as defined in claim 1 wherein said current path comprises one of a transmission line and a resistor.

Claim 7

A semiconductor integrated circuit as defined in claim 1 wherein said field effect transistor is a high frequency switch.

Claim 8

A semiconductor integrated circuit as defined in claim 1 wherein said auxiliary current path comprises a resistor including a refractory metal silicide which is produced on a semi-insulating film on the substrate, or a resistor produced by an ion implantation at a surface portion of said substrate.

Claim 9

A semiconductor integrated circuit as defined in claim 1 including an electrode layer spaced from at least one of said source and said drain and electrically connected through a second current path to one of said source and drain wherein said via-hole is disposed directly opposite said electrode layer.

Claim 10

A semiconductor integrated circuit comprising: a semi-insulating semiconductor substrate having opposed front and rear surfaces; a field effect transistor disposed on the front surface of said semi-insulating semiconductor substrate having a source, a gate, and a drain, said gate having an impedance; a rear surface electrode disposed on the rear surface of said semi-insulating semiconductor substrate; a gate bias bonding pad disposed on the front surface of said semi-insulating semiconductor substrate and electrically connected to said gate for applying a bias to said gate of said field effect transistor; a current path electrically connecting said gate bias bonding pad and said gate and having substantially the same impedance as said gate; an electrically conducting via-hole extending through said semi-insulating semiconductor substrate connecting one of the source and drain of said field effect transistor with said rear surface electrode; and an auxiliary current path electrically connecting said current path with said rear surface electrode, said auxiliary current path comprising a wiring on the front surface of said semi-insulating semiconductor substrate making an ohmic contact with said semi-insulating semiconductor substrate.

Claim 11

A semiconductor integrated circuit comprising: a semi-insulating semiconductor substrate having opposed front and rear surfaces; a field effect transistor disposed on the front surface of said semi-insulating semiconductor substrate having a source, a gate, and a drain, said gate having an impedance; a rear surface electrode disposed on the rear surface of said semi-insulating semiconductor substrate; a gate bias bonding pad disposed on the front surface of said semi-insulating semiconductor substrate and electrically connected to said gate for applying a bias to said gate of said field effect transistor; a current path electrically connecting said gate bias bonding pad and said gate and having substantially the same impedance as said gate; an electrically conducting via-hole extending through said semi-insulating semiconductor substrate connecting one of the source and drain of said field effect transistor with said rear surface electrode; and an auxiliary current path electrically connecting said current path with said rear surface electrode, said auxiliary current path comprising a wiring on the front surface of said semi-insulating semiconductor substrate making an ohmic contact with said semi-insulating semiconductor substrate.

Claim 12

A semiconductor integrated circuit as defined in claim 9 comprising an active layer disposed at the front surface of said semi-insulating semiconductor substrate wherein said source and drain are disposed on said active layer and said gate is disposed between said source and said drain.

Claim 13

A semiconductor integrated circuit as defined in claim 9 wherein said substrate has a resistance and said wiring has a sufficiently large area that the resistance between the gate and the rear surface electrode is a small as the substrate resistance.