US5170374A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor memory
Assignee: Renesas Technology Corp
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Filing: 1992-04-07
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Granted: 1992-12-08
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Expires: 2012-04-07
Abstract
Abstract A dynamic RAM integrated circuit of the one-element memory cell type is provided with a plurality of data lines, a sense amplifier, a plurality of word lines disposed in a manner to intersect with the data lines, and memory cells disposed at the points of intersection between the data lines and the word lines. The RAM includes a P-type semiconductor substrate and an N-type well region formed in the substrate. The memory cells are disposed within the well, and the sense amplifier, which is connected to the date lines, is constructed of a pair of N-channel MOSFETs formed in the semiconductor substrate and a pair of P-channel MOSFETs formed in the well region.
Inventors
- 👤 Katsuhiro Shimohigashi
- 👤 Hiroo Masuda
- 👤 Kunihiko Ikuzaki
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 14:43
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/409; G11C11/4091; G11C11/4096; G11C11/4097; H; H10; H10B; H10B12/00; H10B12/30; H10W; H10W20/00; H10W20/40
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
441 words
A semiconductor memory formed in a semiconductor integrated circuit comprising: a pair of data lines disposed substantially parallel and adjacent to each other; a plurality of word lines, each of which is arranged so as to intersect with both of said pair of data lines; a plurality of memory cells, each of which is coupled to one of said word lines and one of said pair of data lines at a cross point thereof; an amplifier coupled to said pair of data lines for amplifying a potential difference with exists between said data lines, said amplifier comprising first and second circuits; wherein said circuit includes a first MISFET of a first conductivity type having its drain coupled to one of said pair of data lines and its gate coupled to the other of said pair of data lines, a second MISFET of said first conductivity type having its drain coupled to said gate of said first MISFET, its gate coupled to said drain of said first MISFET and its source coupled to a source of said first MISFET, a third MISFET of said first conductivity type having its drain coupled to said source of said first MISFET, its source supplied with a first power source voltage and its gate supplied with a first timing signal, and a fourth MISFET of said first conductivity type having its drain coupled to said source of said first MISFET, its source supplied with said first power source voltage and its gate supplied with a second timing signal; and wherein said second circuit includes a fifth MISFET of a second conductivity type having its drain coupled to one of said pair of data lines and its gate coupled to the other of said pair of data lines, a sixth MISFET of said second conductivity type having its drain coupled to said gate of said fifth MISFET, its gate coupled to said drain of said fifth MISFET and its source coupled to a source of said fifth MISFET, and a seventh MISFET of said second conductivity type having its drain coupled to said source of said fifth MISFET, its source supplied with a second power source voltage and its gate supplied with a third timing signal, wherein said third MISFET is turned "on" in response to said first timing signal at a time different from a time when said fourth MISFET is turned "on" in response to said second timing signals, and wherein said seventh MISFET is turned "on" in response to said third timing signal at a time different from said time when said fourth MISFET is turned "on" in response to said second timing signals.
Claim 2
Dependent Claim
441 words
A semiconductor memory formed in a semiconductor integrated circuit comprising: a pair of data lines disposed substantially parallel and adjacent to each other; a plurality of word lines, each of which is arranged so as to intersect with both of said pair of data lines; a plurality of memory cells, each of which is coupled to one of said word lines and one of said pair of data lines at a cross point thereof; an amplifier coupled to said pair of data lines for amplifying a potential difference with exists between said data lines, said amplifier comprising first and second circuits; wherein said circuit includes a first MISFET of a first conductivity type having its drain coupled to one of said pair of data lines and its gate coupled to the other of said pair of data lines, a second MISFET of said first conductivity type having its drain coupled to said gate of said first MISFET, its gate coupled to said drain of said first MISFET and its source coupled to a source of said first MISFET, a third MISFET of said first conductivity type having its drain coupled to said source of said first MISFET, its source supplied with a first power source voltage and its gate supplied with a first timing signal, and a fourth MISFET of said first conductivity type having its drain coupled to said source of said first MISFET, its source supplied with said first power source voltage and its gate supplied with a second timing signal; and wherein said second circuit includes a fifth MISFET of a second conductivity type having its drain coupled to one of said pair of data lines and its gate coupled to the other of said pair of data lines, a sixth MISFET of said second conductivity type having its drain coupled to said gate of said fifth MISFET, its gate coupled to said drain of said fifth MISFET and its source coupled to a source of said fifth MISFET, and a seventh MISFET of said second conductivity type having its drain coupled to said source of said fifth MISFET, its source supplied with a second power source voltage and its gate supplied with a third timing signal, wherein said third MISFET is turned "on" in response to said first timing signal at a time different from a time when said fourth MISFET is turned "on" in response to said second timing signals, and wherein said seventh MISFET is turned "on" in response to said third timing signal at a time different from said time when said fourth MISFET is turned "on" in response to said second timing signals.
Claim 3
Dependent Claim
48 words
A semiconductor memory according to claim 1, wherein an amplification operation of said first circuit is started in response to turning "on" of said third or fourth MISFETs, and wherein an amplification operation of said second circuit is started in response to turning "on" of said seventh MISFET.
Claim 4
Dependent Claim
28 words
A semiconductor memory according to claim 2, wherein said first, second, third and fourth MISFETs are N-channel MISFETs and said fifth, sixth and seventh MISFETs are P-channel MISFETs.
Claim 5
Dependent Claim
36 words
A semiconductor memory according to claim 3, wherein said fourth MISFET is turned "on" after said third MISFET is turned "on", and wherein said seventh MISFET is turned "on" after said fourth MISFET is turned "on".
Claim 6
Dependent Claim
29 words
A semiconductor memory according to claim 4, wherein said first power source voltage corresponds to a ground potential and said second power source voltage corresponds to a positive potential.
Claim 7
Dependent Claim
23 words
A semiconductor memory according to claim 5, wherein a conductance of said third MISFET is smaller than a conductance of said fourth MISFET.
Claim 8
Dependent Claim
33 words
A semiconductor memory according to claim 6, further comprising means for charging said pair of data lines at a potential intermediate between said first power source voltage and said second power source voltage.
Claim 9
Dependent Claim
57 words
A semiconductor memory according to claim 7, further comprising selecting means coupled to said plurality of word lines for placing one of said plurality of word lines in a selected state, wherein said potential difference between said data lines is generated in response to selection of one of said plurality of word lines by said selecting means.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-12-08 | 1996-06-08 | 1996-12-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-12-08 | 2000-06-08 | 2000-12-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-12-08 | 2004-06-08 | 2004-12-08 | $7700.00 | Window Closed / Lapsed |