Semiconductor memory device having means for replacing defective memory cells

Claim 2

A semiconductor memory device, comprising: first memory means being a first type of memory which includes memory cells for prestoring fixed data; decoder means for decoding an input address and for reading out a fixed data from said first memory means based on a decoded input address; second memory means being a second type of memory for storing a data identical to that prestored in a defective memory cell of said first memory means, wherein said second memory means can replace a defective memory cell within said first memory means, and includes programmable non-volatile memory cells; discriminating means operably connected to said first memory means including third memory means for storing a redundant address corresponding to each defective memory cell of said first memory means, wherein said discriminating means discriminates whether or not the input address coincides with the redundant address and outputs a discrimination signal when the input address coincides with the redundant address; and selecting means operably connected to said first and second memory means, said selecting means being supplied with data read out from said first and second memory means for normally outputting the data read out from said first memory means and for selectively outputting the data from said second memory means when the discrimination signal is received from said discriminating means.

Claim 3

The semiconductor memory device as claimed in claim 1 wherein, said first memory means comprises a mask read only memory cell array, and said second memory means comprises a programmable read only memory cell array.

Claim 4

The semiconductor memory device as claimed in claim 1 wherein, said third memory means comprises a first memory for storing a redundant address of each row or column which includes the defective memory cell of said first memory means and a second memory for storing a direction information which designates a replacing direction in which the defective memory cell of said first memory means is to be replaced, an address switch means for selectively extracting an address for decoding to be used in the second memory means and an address for discriminating the replacement of the defective memory cell in the first memory means when the input address includes the defective address based on the direction information which is obtained from the second memory.

Claim 5

The semiconductor memory device as claimed in claim 1 wherein, said first memory means comprises a plurality of cell blocks respectively having a plurality of memory cells, each of said cell blocks outputting a multi-bit data when designated by the input address, said discriminating means outputting a discrimination signal when the input address coincides with a redundant address of the defective memory cell within one of the cell blocks.

Claim 6

The semiconductor memory device as claimed in claim 4 wherein, the memory cells of said first memory means are respectively coupled to a corresponding one of word lines and a corresponding one of bit lines, and only one word line of an arbitrary cell block is activated when the arbitrary memory cell thereof is designated by the input address.

Claim 7

The semiconductor memory device as claimed in claim 1 wherein, the memory cells of said second memory means are respectively coupled to a corresponding one of word lines and a corresponding one of bit lines, each memory cell of said second memory means comprising a first metal insulator semiconductor transistor having one of a source and a drain connected to one bit line and a first capacitor having a first electrode connected to a gate of said first metal insulator semiconductor transistor and a second electrode connected to one word line.

Claim 8

The semiconductor memory device as claimed in claim 6 wherein, each memory cell of said third memory means comprises a second metal insulator semiconductor transistor and a second capacitor having one electrode connected to a gate of said second metal insulator semiconductor transistor.

Claim 9

The semiconductor memory device as claimed in claim 6 wherein, said first memory means comprises a mask read only memory cell array.

Claim 10

The semiconductor memory device as claimed in claim 6 wherein, the memory cells of said first memory means are arranged with a first pitch, and the memory cells of said second memory means are arranged with a second pitch, said first pitch being smaller than said second pitch.

Claim 11

The semiconductor memory device as claimed in claim 9 wherein, the memory cells of said second memory means are arranged in series as m columns which are parallel to the bit lines, each column comprising 1/n a number of memory cells in a corresponding column of said first memory means, m and n being arbitrary integers.

Claim 12

The semiconductor memory device as claimed in claim 9 wherein, the memory cells of said second memory means are arranged in series as M rows which are parallel to the word lines, each row comprising 1/N a number of memory cells in a corresponding row of said first memory means, M and N being arbitrary integers.

Claim 13

The semiconductor memory device as claimed in claim 1 wherein, said first memory means comprises a plurality of memory cells which are arranged in rows and columns and outputs a multi-bit data when designated by the input address, said third memory means stores a redundant address of each row or column of said first memory means which includes a defective memory cell of said first memory means, and said selecting means replaces at least a portion of the data read out from said first memory means by a corresponding portion of the data from said second memory means when the discrimination signal is received from said discriminating means.

Claim 14

The semiconductor memory device as claimed in claim 12 wherein, said selecting means comprises bit storage means for storing predetermined bits of the data read out from said first memory means and to be replaced, and replacement means for replacing the predetermined bits of the data read out from said first memory means by corresponding bits of the data from said second memory means when the discrimination signal is received from said discriminating means based on the predetermined bits stored in said bit storage means.

Claim 15

The semiconductor memory device as claimed in claim 1 wherein, said first memory means comprises a plurality of memory cells which are arranged in rows and columns, said third memory means stores a redundant address of rows and columns of said first memory means which include a defective memory cell, and said selecting means replaces the data read out from said first memory means by the data from at least one of a corresponding row and column of said second memory means when the redundant address spans two adjacent rows or columns of said first memory means and the discrimination signal is received from said discriminating means.

Claim 16

The semiconductor memory device as claimed in claim 14 wherein, said discriminating means includes adding means for adding an integer L to the redundant address stored in said third memory means, and comparing means for outputting the discrimination signal when the input address coincides with one of the addresses received from said adding means and said third memory means.

Claim 17

The semiconductor memory device as claimed in claim 15 wherein, the addresses which are output from said third memory means and said adding means respectively designate one block, each block being made up of at least one row of said first memory means.

Claim 18

The semiconductor memory device as claimed in claim 15 wherein, the addresses which are output from said third memory means and said adding means respectively designate one block, each block being made up of at least one column of said first memory means.

Claim 19

The semiconductor memory device as claimed in claim 14 wherein, said first memory means comprises a mask read only memory cell array.

Claim 20

The semiconductor memory device as claimed in claim 14 wherein, said first memory means comprises a memory cell array selected from a group which includes a dynamic random access memory, an erasable programmable read only memory and a mask read only memory.

Claim 21

A semiconductor memory device, comprising: first memory means including memory cells for prestoring fixed data; decoder means for decoding an input address and for reading out a fixed data from said first memory means based on a decoded input address; second memory means for storing a data identical to that prestored in a defective memory cell of said first memory means, wherein said second memory means includes programmable non-volatile memory cells; discriminating means including third memory means for storing a redundant address corresponding to each defective memory cell of said first memory means for discriminating whether or not the input address coincides with the redundant address and for outputting a discrimination signal when the input address coincides with the redundant address; and selecting means supplied with data read out from said first and second memory means for normally outputting the data read out from said first memory means and for selectively outputting the data from said second memory means when the discrimination signal is received from said discriminating means, wherein said first memory means comprises a plurality of memory cells which are arranged in rows and columns, said third memory means storing a redundant address of rows and columns of said first memory means which include a defective memory cell, and said selecting means replacing the data read out from said first memory means by the data from at least one of a corresponding row and column of said second memory means when the redundant address spans two adjacent rows or columns of said first memory means and the discrimination signal is received from said discriminating means, and wherein said discriminating means includes adding means for adding an integer L to the redundant address stored in said third memory means, and comparing means for outputting the discrimination signal when the input address coincides with one of the addresses received from said adding means and said third memory means.

Claim 22

A semiconductor memory device, comprising: first memory means including memory cells for prestoring fixed data; decoder means for decoding an input address and for reading out a fixed data from said first memory means based on a decoded input address; second memory means for storing a data identical to that prestored in a defective memory cell of said first memory means, wherein said second memory means includes programmable non-volatile memory cells; discriminating means including third memory means for storing a redundant address corresponding to each defective memory cell of said first memory means for discriminating whether or not the input address coincides with the redundant address and for outputting a discrimination signal when the input address coincides with the redundant address; and selecting means supplied with data read out from said first and second memory means for normally outputting the data read out from said first memory means and for selectively outputting the data from said second memory means when the discrimination signal is received from said discriminating means, wherein said first memory means comprises a plurality of memory cells which are arranged in rows and columns, said third memory means storing a redundant address of rows and columns of said first memory means which include a defective memory cell, and said selecting means replacing the data read out from said first memory means by the data from at least one of a corresponding row and column of said second memory means when the redundant address spans two adjacent rows or columns of said first memory means and the discrimination signal is received from said discriminating means, and wherein said discriminating means includes adding means for adding an integer L to the redundant address stored in said third memory means, and comparing means for outputting the discrimination signal when the input address coincides with one of the addresses received from said adding means and said third memory means.

Claim 23

The semiconductor memory device as claimed in claim 20, wherein the addresses which are output from said third memory means and said adding means respectively designate one block, each block being made up of at least one row of said first memory means.

Claim 24

The semiconductor memory device as claimed in claim 20, wherein the addresses which are output from said third memory means and said adding means respectively designate one block, each block being made up of at least one column of said first memory means.