Programmable logic device with limited signal swing

Claim 1

A programmable logic device, comprising: (a) a first bit line; (b) a plurality of memory cells, each having a drain, a source, a floating gate, and a control gate, wherein the drain of each of the plurality of memory cells is coupled to the first bit line; (c) a second bit line coupled to the source of each of the plurality of memory cells; (d) a sensing amplifier coupled to the first bit line for sensing voltage level of the first bit line; (e) current controlling means coupled to the second bit line and the first bit line for limiting current flow on the first bit line, wherein when the voltage level swings from a first voltage state to a second voltage state, the current controlling means limits the current flow on the first bit line to a predetermined current limit; and (f) means for clamping the voltage level of the first bit line to swing between the first voltage state and the second voltage state, wherein the clamping means is coupled to the first bit line, wherein when the voltage level approaches the second voltage state, the clamping means provides current to the first bit line, wherein when the voltage level approaches the first voltage state, the clamping means receives current from the first bit line.