Processing system for branch instruction

Claim 1

A processing system for executing a stored program of instructions including dedicated decoding and execution means for processing branch instructions, comprising: a memory for storing instructions including a branch instruction and a branch destination instruction and responsive to first and second address signals for supplying said instructions; an instruction pre-fetch address register storing a periodically-updated first address and supplying said first address to said memory for reading the instructions from the memory; a branch instruction pre-fetch address register storing a second address and supplying said second address to said memory and to said instruction pre-fetch address register for reading the branch destination instruction from the memory; a first execution unit including an instruction decoder for providing execution control signals in response to decoding said instruction; an instruction buffer receiving said instructions from said memory and sequentially storing the instructions from the memory by use of the periodically-updated address in the instruction pre-fetch address register, the instruction buffer supplying the sequentially stored instructions to the first execution unit, the first execution unit decoding the instructions supplied by the instructions buffer to supply decoded instruction commands; a branch instruction buffer receiving one of said instructions from said memory and storing the instruction which is read from the memory by use of the branch destination address in the branch instruction pre-fetch address register, the branch instruction buffer supplying the branch destination instruction to the first execution unit, the first execution unit decoding the instruction supplied by the branch instruction buffer to supply said control signals; a calculator for calculating the branch destination address; said decoder including an instruction control circuit for decoding instructions supplied by said instruction buffer and, detecting a branch instruction and, in response, selectively supplying commands for transferring said instruction to a second execution unit and supplying a control signal to said second execution unit for calculating said branch destination address; and said second execution unit for executing the commands generated by the instruction control circuit; wherein the instruction control circuit is operative to detect a conditional branch instruction; wherein when the instruction control circuit detects the conditional branch instruction, the instruction control circuit (i) prevents a command of the conditional branch instruction from being transferred to the second execution unit, (ii) enables the calculation of the branch destination address by the calculator, (iii) stores a result of the calculation into the branch instruction pre-fetch address register, (iv) reads the branch destination instruction corresponding to the branch destination address from the memory, (v) stores the branch destination instruction into the branch destination buffer, (vi) interrupts decoding until execution of the instructions decoded prior to the conditional branch instruction is completed, (vii) waits for a determination of a result of calculation, (viii) determines whether establishment of a branch is present or absent after the result is determined, and (ix) selectively (a) disables (I) the decoded instructions which follow the conditional branch instruction and (II) generation of a command after decoding of the branch destination instruction stored in the branch destination instruction buffer and (III) transfer of the command to the execution unit in cases where the branch is established, or (b) causes execution of the commands of the decoded instructions which follow the branch instruction by the second execution unit in cases where the branch is not established.