Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
258 words
A read-only memory device for storing programmed data and subsequently reading out the stored data, comprising a plurality of memory cells arranged in rows and columns in a matrix configuration and including MIS (metal insulated semiconductor) transistors which may be selectively set to a high threshold voltage or to a low threshold voltage in accordance with programmed data, a plurality of word lines used in common in each row of said cells and connected to gates of said MIS transistors, a plurality of bit lines arranged substantially orthogonally to said word lines, said bit lines connected as one of the sources or the drains of said MIS transistors and being used in common for data read-out by one of adjacent columns of said memory cells, a plurality of column lines arranged between said bit lines in alternation with and parallel to said bit lines, said column lines being used in common by the other of adjacent columns of said memory cells and functioning as the other of said sources or drains of said MIS transistors of columns of said cells, a potential difference higher than said low threshold voltage and lower than said high threshold voltage of said MIS transistor being applied on selection with respect to the voltage at said word line, first selection means for selecting groups each consisting of a plurality of said bit lines and a plurality of said column lines, second selection means for selecting said bit lines in each group, and third selection means for selecting said column lines in each group.
Claim 2
Dependent Claim
258 words
A read-only memory device for storing programmed data and subsequently reading out the stored data, comprising a plurality of memory cells arranged in rows and columns in a matrix configuration and including MIS (metal insulated semiconductor) transistors which may be selectively set to a high threshold voltage or to a low threshold voltage in accordance with programmed data, a plurality of word lines used in common in each row of said cells and connected to gates of said MIS transistors, a plurality of bit lines arranged substantially orthogonally to said word lines, said bit lines connected as one of the sources or the drains of said MIS transistors and being used in common for data read-out by one of adjacent columns of said memory cells, a plurality of column lines arranged between said bit lines in alternation with and parallel to said bit lines, said column lines being used in common by the other of adjacent columns of said memory cells and functioning as the other of said sources or drains of said MIS transistors of columns of said cells, a potential difference higher than said low threshold voltage and lower than said high threshold voltage of said MIS transistor being applied on selection with respect to the voltage at said word line, first selection means for selecting groups each consisting of a plurality of said bit lines and a plurality of said column lines, second selection means for selecting said bit lines in each group, and third selection means for selecting said column lines in each group.
Claim 3
Dependent Claim
18 words
The read-only memory device according to claim 1, wherein said second and third selection means comprise MIS transistors.
Claim 4
Dependent Claim
54 words
The read-only memory device according to claim 2, wherein said bit lines and said column lines are formed in a striped pattern on a substrate and wherein a direction substantially orthogonal to the longitudinal direction of said striped pattern is the channel direction of said MIS transistors constituting said second and third selection means.
Claim 5
Dependent Claim
32 words
The read-only memory device according to claim 1 or 3, wherein said second selection means is arranged in opposition to said third selection means with an array of said memory cells inbetween.
Claim 6
Dependent Claim
37 words
The read-only memory device according to claim 1, wherein said memory cells in the matrix configuration are divided into blocks along the bit lines and wherein said first selection means are used in common in each block.
Claim 7
Dependent Claim
24 words
The read-only memory device according to claim 1, wherein load circuits are arranged at terminal ends of each bit line and each column line.
Claim 8
Dependent Claim
36 words
The read-only memory device according to claim 6, wherein said memory cells in the matrix configuration are divided into blocks along the bit lines and wherein the load circuits are used in common by each block.