US5204957A
Expired / Lapsed
US
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Integrated circuit timer with multiple channels and dedicated service processor
Assignee: Motorola Solutions Inc
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Filing: 1992-09-30
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Granted: 1993-04-20
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Expires: 2012-09-30
Abstract
Abstract A timer system comprises multiple channels, each of which is capable of performing input and output timer functions referenced to any of a plurality of timer reference signals. In the preferred embodiment, sixteen independent channels are serviced by a processor dedicated to that purpose and each can perform capture and match functions referenced to either of two free-running counters.
Inventors
- 👤 Brian F. Wilkie
- 👤 Vernon B. Goler
- 👤 Stanley E. Groves
- 👤 John J. Vaglica
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 13:48
CPC Classifications
G; G04; G04G; G04G99/00; G04G3/00; G06; G06F; G06F1/00; G06F1/04; G06F1/14
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
176 words
A microprocessor comprising: a first memory; a first bus coupled to the first memory; a first processing unit coupled to the first bus, the first processing unit is capable of executing instructions stored in the first memory; a second bus coupled to the first memory; and a timer unit, the timer unit further comprising: a) a second memory; b) a third bus coupled to the second memory; c) a second processing unit coupled to the second bus and to the third bus, the second processing unit is capable of executing instructions stored in the first memory and is also capable of executing instructions stored in the second memory; d) a third memory coupled to the first bus; e) a fourth bus coupled to the third memory and to the second processing unit; and f) timer logic, the timer logic further comprising: i) pin logic coupled to a pin of the microprocessor; ii) an event register coupled to the pin logic; and iii) a fifth bus coupled to the event register and to the second processing unit.
Claim 2
Dependent Claim
176 words
A microprocessor comprising: a first memory; a first bus coupled to the first memory; a first processing unit coupled to the first bus, the first processing unit is capable of executing instructions stored in the first memory; a second bus coupled to the first memory; and a timer unit, the timer unit further comprising: a) a second memory; b) a third bus coupled to the second memory; c) a second processing unit coupled to the second bus and to the third bus, the second processing unit is capable of executing instructions stored in the first memory and is also capable of executing instructions stored in the second memory; d) a third memory coupled to the first bus; e) a fourth bus coupled to the third memory and to the second processing unit; and f) timer logic, the timer logic further comprising: i) pin logic coupled to a pin of the microprocessor; ii) an event register coupled to the pin logic; and iii) a fifth bus coupled to the event register and to the second processing unit.
Claim 3
Dependent Claim
30 words
A microprocessor according to claim 1 wherein the second processing unit further comprises: i) a counter; and ii) a sixth bus coupled to the counter and to the event register.
Claim 4
Dependent Claim
55 words
A microprocessor according to claim 2 wherein the timer means further comprises: iv) capture means for storing in the event register a value of the counter in response to an event occurring at the pin; and v) match means for continuously comparing a value contained in the event register to a value of the counter.
Claim 5
Dependent Claim
183 words
A microprocessor comprising: a first memory; a first bus coupled to the first memory; a first processing unit coupled to the first bus, the first processing unit is capable of executing instructions stored in the first memory; a second bus coupled to the first memory; and a timer unit, the timer unit further comprising: a) a second memory; b) a third bus coupled to the second memory; c) a second processing unit coupled to the second bus and to the third bus, the second processing unit is capable of executing instructions stored in the first memory and is also capable of executing instructions stored in the second memory; d) a third memory coupled to the first bus; e) a fourth bus coupled to the third memory and to the second processing unit; and f) a plurality of timer channels, each of said plurality of timer channels further comprising: i) pin logic coupled to a pin of the microprocessor; ii) an event register coupled to the pin logic; and iii) a fifth bus coupled to the event register and to the second processing unit.
Claim 6
Dependent Claim
183 words
A microprocessor comprising: a first memory; a first bus coupled to the first memory; a first processing unit coupled to the first bus, the first processing unit is capable of executing instructions stored in the first memory; a second bus coupled to the first memory; and a timer unit, the timer unit further comprising: a) a second memory; b) a third bus coupled to the second memory; c) a second processing unit coupled to the second bus and to the third bus, the second processing unit is capable of executing instructions stored in the first memory and is also capable of executing instructions stored in the second memory; d) a third memory coupled to the first bus; e) a fourth bus coupled to the third memory and to the second processing unit; and f) a plurality of timer channels, each of said plurality of timer channels further comprising: i) pin logic coupled to a pin of the microprocessor; ii) an event register coupled to the pin logic; and iii) a fifth bus coupled to the event register and to the second processing unit.
Claim 7
Dependent Claim
38 words
A microprocessor according to claim 4 wherein the second processing unit further comprises: i) a counter; and ii) a sixth bus coupled to the counter and to the event register of each of the plurality of timer channels.
Claim 8
Dependent Claim
59 words
A microprocessor according to claim 5 wherein each of the plurality of timer channels further comprises: iv) capture means for storing in the event register a value of the counter in response to an event occurring at the pin; and v) match means for continuously comparing a value contained in the event register to a value of the counter.
Claim 9
Dependent Claim
36 words
A microprocessor according to claim 6 wherein each of the timer channels further comprises: vi) service request means for generating a service request signal and for communicating the service request signal to the second processing unit.
Claim 10
Dependent Claim
42 words
A microprocessor according to claim 7 wherein the timer unit further comprises: g) scheduler means for receiving the service request signals from each of the plurality of timer channels' service request means, the scheduler means is coupled to the second processing unit.
Claim 11
Dependent Claim
105 words
A microprocessor according to claim 8 wherein the third memory further comprises: i) a first memory portion coupled to the scheduler means and writable by the first processing unit by means of the first bus, the first memory portion further comprises a plurality of channel priority fields equal in number to the number of the plurality of timer channels; and wherein the scheduler means further comprises: i) means responsive to the service request signals from each of the plurality of timer channels' service request means and to values stored in each of the channel priority fields to select one of the plurality of timer channels.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-04-19 | 1996-10-19 | 1997-04-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-04-19 | 2000-10-19 | 2001-04-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-04-19 | 2004-10-19 | 2005-04-20 | $7700.00 | Window Closed / Lapsed |