Processor with preceding operation circuit connected to output of data register

Claim 2

A processor comprising: control signal generation means for generating a control signal, first operating means responsive to the control signal for carrying out a first operation designated by the control signal, data bus lines connected to said first operating means for transmitting data used for the first operation by said first operating means, holding means connected to said data bus lines for holding data used for the first operation by said first operating means and responsive to said control signal to supply said data to said data bus lines, and second operating means continuously receiving an output of said holding means for carrying out a predetermined second operation in response to storage of said data in said holding means, said second operating means being responsive to the control signal to supply data indicative of the result of the second operation to said data bus lines.

Claim 3

The processor according to claim 1, wherein said first operating means being further responsive to said control signal for carrying out said predetermined second operation, and said second operating means is responsive to the control signal to perform said second operation and to supply data indicative of the result of the second operation to said first operating means through said data bus lines, thereby to reduce time required by said first means to carry out said second operation.

Claim 4

The processor according to claim 1, wherein said holding means comprises storage means connected to said data bus lines for storing data used for the first operation by said first operating means, and said storage means is responsive to the control signal for applying the stored data to said second operating means.

Claim 5

The processor according to claim 1, wherein said holding means comprises first and second registers for holding data used for the first operation by said first operating means said first and second registers being connected to said data bus lines.

Claim 6

The processor according to claim 4, wherein said second operating means comprises adding means connected to outputs of said first and second registers for carrying out a predetermined addition operation.

Claim 7

The processor according to claim 4, wherein said second operating means comprises subtracting means connected to outputs of said first and second registers for carrying out a predetermined subtraction operation.

Claim 8

The processor according to claim 4, wherein said second operating means comprises comparison means connected to outputs of said first and second registers for carrying out a predetermined comparison operation.

Claim 9

The processor according to claim 1, wherein said holding means comprises a single register connected to said data bus lines for holding data used in said second operating means.

Claim 10

A processor comprising: control signal generation means for generating a control signal to control the designation and execution of a first operation, first operating means responsive to the control signal for carrying out the first operation designated by the control signal, data bus lines connected to said first operating means for transmitting data used for the first operation by said first operating means, holding means connected to said data bus lines for holding data used for the first operation by said first operating means, and second operating means connected to an output of said holding means for carrying out a predetermined second operation, said holding means comprising a single register connected to said data bus lines for holding data used in said second operating means, said second operating means being responsive to the control signal to supply data indicative of the result of the second operation to said data bus lines, wherein said second operating means comprises sign inverter means connected to the output of said single register for inverting the sign of output data from said single register.

Claim 11

A processor comprising: control signal generation means for generating a control signal to control the designation and execution of a first operation, first operating means responsive to the control signal for carrying out the first operation designated by the control signal, data bus lines connected to said first operating means for transmitting data used for the first operation by said first operating means, holding means connected to said data bus lines for holding data used for the first operation by said first operating means, and second operating means connected to an output of said holding means for carrying out a predetermined second operation, said holding means comprising a single register connected to said data bus lines for holding data used in said second operating means, said second operating means being responsive to the control signal to supply data indicative of the result of the second operation to said data bus lines, wherein said second operating means comprises sign inverter means connected to the output of said single register for inverting the sign of output data from said single register.

Claim 12

The processor according to claim 1, wherein said control signal generation means further generates data used by said second operating means, and said second operating means receives data held in said holding means and data generated from said control signal generation means, and carries out said predetermined second operation.

Claim 13

The processor according to claim 1, wherein said holding means comprises n registers each connected to said data bus lines for holding n data applied through said data bus lines and used for the second operation in said second operating means, said n comprising an integer above two, said second operating means comprising summing means connected to each of said n registers for summing output data from said n registers.

Claim 14

The processor according to claim 1, wherein said first operating means comprises one of an arithmetic and logic unit and a multiplier connected to said data bus lines.

Claim 15

The processor according to claim 1, wherein said control signal generation means comprises: program storage means for storing a program and having an output for outputting the program to instruct execution of said first operation, and decoding means connected to said program storage means for decoding the program output from said program storage means and outputting a signal obtained by decoding as said control signal.

Claim 16

A processor comprising; control signal generation means for generating a control signal to control the designation and execution of a desired first operation, first operating means responsive to the control signal for carrying out the first operation designated by the control signal, data bus lines connected to said first operating means for transmitting data used for the first operation by said first operating means, holding means connected to said data bus lines for holding first data used for the first operation by said first operating means and responsive to said control signal to supply said data to said data bus lines, data storage means connected to said data bus lines for storing second data used for the first operation by said first operating means, and second operating means continuously receiving an output of said holding means and an output of said data storage means for carrying out a predetermined second operation in responsive to storage of said data in said holding means, said second operating means being responsive to the control signal to supply data indicative of the result of the second operation to said data bus lines.

Claim 17

A processor comprising; control signal generation means for generating a control signal to control the designation and execution of a desired first operation, first operating means responsive to the control signal for carrying out the first operation designated by the control signal, data bus lines connected to said first operating means for transmitting data used for the first operation by said first operating means, holding means connected to said data bus lines for holding first data used for the first operation by said first operating means and responsive to said control signal to supply said data to said data bus lines, data storage means connected to said data bus lines for storing second data used for the first operation by said first operating means, and second operating means continuously receiving an output of said holding means and an output of said data storage means for carrying out a predetermined second operation in responsive to storage of said data in said holding means, said second operating means being responsive to the control signal to supply data indicative of the result of the second operation to said data bus lines.

Claim 18

A processor comprising: data bus lines for transmitting operational data, operating means connected to said data bus lines for operating on the operational data applied from said data bus lines, at least first and second holding means connected to receive output data from said operating means for holding the output data, adding means continuously receiving outputs of said first and second holding means for adding the data held in said first and second holding means, and subtracting means continuously receiving outputs of said first and second holding means for subtracting the data held in said first and second holding means, said adding means and subtracting means having outputs connected to said data bus lines.

Claim 19

A processor comprising: data bus lines for transmitting operational data, operating means connected to said data bus lines for operating on the operational data applied from said data bus lines, at least first and second holding means connected to receive output data from said operating means for holding the output data, adding means continuously receiving outputs of said first and second holding means for adding the data held in said first and second holding means, and subtracting means continuously receiving outputs of said first and second holding means for subtracting the data held in said first and second holding means, said adding means and subtracting means having outputs connected to said data bus lines.

Claim 20

The processor according to claim 15, wherein said operating means comprises multiplying means connected to receive output data from said subtracting means for multiplying the output data from said subtracting means by a value defined in accordance with a predetermined operational formula.

Claim 21

The processor according to claim 15, wherein each of said first and second holding means comprises first and second registers, respectively.

Claim 22

The processor according to claim 16, wherein said predetermined operational formula comprises butterfly operational formula, and said processor further comprises control signal generating means for generating a control signal to carry out butterfly operation, said adding means, subtracting means and multiplying means being responsive to the control signal to carry out each of the operations.

Claim 23

A processor according to claim 18, wherein said control signal generating means comprises; storage means for storing an instruction program to carry out said butterfly operation, and decoding means for decoding the instruction program from said storage means and for outputting said control signal.

Claim 24

The processor according to claim 19, wherein said control signal generating means further comprises designation signal generating means responsive to the output signal from said decoding means for generating a source designation signal to designate said adding means and subtracting means as sources by an operation performed by said operating means.

Claim 25

The processor according to claim 15, comprising a digital signal processor (DSP).

Claim 26

The processor according to claim 1, wherein said first operating means is connected for receiving said data indicative of the result of the second operation from said second operating means through said data bus lines.

Claim 27

In a digital signal processor including an instruction storage means, a program sequence control means responsive to instructions from said instruction storage means for generating control signals, data storage means, address means for addressing data in said data storage means and for generating source and destination addresses for operands and for results of mathematical operations on said operands, data operating means including multiplying means and ALU (arithmetic logic unit) means for performing mathematical operations on data supplied thereto, a plurality of register means for storage of intermediate results of said mathematical operations, and bus means for transfer of signals and data among the plurality of means of said digital signal processor, the improvement comprising: step reducing means for reducing a number of mathematical steps performed by said ALU means in obtaining a result of a predetermined mathematical operation, said step reducing means comprising: preceding operation means for performing a processing step on the intermediate result stored in said register means preliminary to provision of the intermediate result to said ALU means, thereby eliminating a requirement of said ALU means to perform said processing step and saving processing time required of said ALU means to execute said predetermined mathematical operation, said preceding operation means having input means continuously connected to at least one of said register means for continuously receiving said intermediate result therefrom, said preceding operation means initiating performance of said processing step substantially simultaneously with storage of said intermediate result in said register means connected to said input means thereof and responsive to control signals from said address means for transferring a result of said processing step performed thereby to said bus line for provision to said ALU means.

Claim 28

In a digital signal processor including an instruction storage means, a program sequence control means responsive to instructions from said instruction storage means for generating control signals, data storage means, address means for addressing data in said data storage means and for generating source and destination addresses for operands and for results of mathematical operations on said operands, data operating means including multiplying means and ALU (arithmetic logic unit) means for performing mathematical operations on data supplied thereto, a plurality of register means for storage of intermediate results of said mathematical operations, and bus means for transfer of signals and data among the plurality of means of said digital signal processor, the improvement comprising: step reducing means for reducing a number of mathematical steps performed by said ALU means in obtaining a result of a predetermined mathematical operation, said step reducing means comprising: preceding operation means for performing a processing step on the intermediate result stored in said register means preliminary to provision of the intermediate result to said ALU means, thereby eliminating a requirement of said ALU means to perform said processing step and saving processing time required of said ALU means to execute said predetermined mathematical operation, said preceding operation means having input means continuously connected to at least one of said register means for continuously receiving said intermediate result therefrom, said preceding operation means initiating performance of said processing step substantially simultaneously with storage of said intermediate result in said register means connected to said input means thereof and responsive to control signals from said address means for transferring a result of said processing step performed thereby to said bus line for provision to said ALU means.

Claim 29

An improved digital signal processor as recited in claim 23, wherein said preceding operation means is connected to only one of said register means for performing a sign inversion on the intermediate result stored therein.

Claim 30

An improved digital signal processor as recited in claim 23, wherein said preceding operation means is connected to at least three of said register means for obtaining a sum of the intermediate results stored therein.

Claim 31

An improved digital signal processor as recited in claim 23 wherein said input means of said preceding operation means is further connected to receive immediate data written in an operand part of an instruction from said address means for performing said processing step on said intermediate result stored in said register means and on said immediate data from said instruction.

Claim 32

An improved digital signal processor as recited in claim 23 wherein said input means of said preceding operation means is further connected to said data storage means for receiving data stored therein to perform said processing step on intermediate data from said register means and on data from said data storage means.

Claim 33

An improved digital signal processor as recited in claim 23 comprising a plurality of preceding operation means, said plurality of preceding operation means connected in pairs for performing processing steps in a butterfly operation, each pair connected to a respective pair of register means for performing said processing steps on intermediate results respectively stored therein.

Claim 34

An improved digital signal processor as recited in claim 28 wherein each pair of preceding operation means includes a first preceding operation means for performing an addition and a second preceding operation means for performing a subtraction.