Selective call receiver with fast bit synchronizer

Claim 2

A radio communications receiver comprising: receiving means for receiving a radio frequency signal; and signal detecting means for detecting a signal modulated onto said radio frequency signal, the signal having a plurality of digital symbols and received at a predetermined baud rate, the signal detecting means comprising: data clock means for generating a timing signal; phase generating means, responsive to the timing signal, for generating a reference signal having a frequency integerly related to the baud rate, the reference signal comprising a plurality of independent phase signals generated relative to the received signal; transition detecting means responsive to the timing signal for detecting transitions which may occur between symbols and for producing an edge signal in response thereof; counting means, coupled to said transition detecting means and said phase generating means, and having a plurality of phase accumulators, each responsive to the edge signal and one of the phase signals which is selectively coupled thereto for accumulating an edge signal count when the edge signal coincides with the phase signal selectively coupled thereto, said counting means further including totalizing means for accumulating a total edge signal count of the number of edge signals detected with a fixed integration time interval; controlling means for initializing said counting means and for enabling said counting means for the fixed integration time interval and for generating a completion signal at the end of the fixed integration time interval; and analyzing means coupled to said counting means and including memory means for storing at least one table of predetermined threshold values corresponding to each of a plurality of total edge signal counts, said analyzing means responsive to the completion signal for selecting from said memory means a threshold value corresponding to the total edge signal count accumulated, and for producing a detect signal in response to the threshold value selected being exceeded by at least one of the edge signal counts accumulated within one of the plurality of phase accumulators.

Claim 3

The receiver of claim 1 wherein said phase generating means generates a reference signal having four phases, each of the four phases corresponding to one fourth of a digital symbol.

Claim 4

The receiver of claim 2 wherein said counting means has four phase accumulators and wherein each phase accumulator corresponds to one of the four phases of the reference signal.

Claim 5

The receiver of claim 1 wherein said transition detecting means, being responsive to the timing signal, for first sampling the state of the received signal in coincidence with a phase signal, and for subsequently sampling the received signal in coincidence with a subsequent phase signal, for detecting a transition in response to a difference between the first and subsequent samples.

Claim 6

The receiver of claim 1 wherein the detect signal includes information corresponding to the phase signal which exceeds the selected threshold value, said data clock means being responsive to the detect signal for providing the timing signal at the baud rate for sampling each symbol, wherein the phase of the timing signal is established in response to the detect signal.

Claim 7

The receiver of claim 5 wherein the timing signal phase is adjusted to be substantially 180 degrees out of phase with the corresponding phase signals producing the detect signal.

Claim 8

The receiver of claim 1 wherein said analyzing means produces the detect signal in response to the threshold value being exceeded by a sum of edge signal counts accumulated within any predetermined number of phase accumulators which correspond to adjacent phase signals of the reference signal.

Claim 9

The receiver of claim 7 wherein said counting means has four phase accumulators and wherein each phase accumulator corresponds to one of the four phases of the reference signal, and said analyzing means produces the detect signal in response to the threshold value being exceeded by the sum of edge signal counts accumulated within any two phase accumulators which correspond to two adjacent phases of the reference signal.

Claim 10

The receiver of claim 7 wherein said data clock means is responsive to the detect signal for providing a timing signal at the baud rate for sampling each symbol, and wherein the timing signal is phase adjusted to be substantially 180 degrees out of phase with the corresponding adjacent phase signals producing the detect signal.

Claim 11

The receiver of claim 7 wherein said data clock means is responsive to the detect signal for providing a timing signal at the baud rate for sampling each symbol, and wherein the timing signal is phase adjusted to be substantially 180 degrees out of phase with the function of the edge signal counts accumulated within said phase accumulators.

Claim 12

The receiver of claim 1 wherein said signal detecting means further includes a mean for dividing the integration time by a constant coupled to the controlling means, said means comprising: selecting means for selecting the constant; and dividing means for dividing the edge signal counts accumulated in said counting means by the constant in response to the completion signal.

Claim 13

The receiver of claim 11 further comprising a code plug means storing information signals indicative of a particular constant, and wherein said selecting means selects the constant in response to the stored information signals.

Claim 14

The receiver of claim 1 wherein the memory means of said analyzing means stores a plurality of threshold tables, each threshold table having a plurality threshold values, each threshold value corresponding to at least one total edge count signal accumulation, and wherein said analyzing means further comprises selecting means for selecting one of the plurality of threshold tables, wherein said selecting means selects the threshold value from the selected threshold table, wherein the selected threshold value corresponding to the total edge count signal accumulation.

Claim 15

The receiver of claim 13 further comprising a code plug means storing information signals for selecting a particular threshold table, wherein said selecting means selects the threshold table in response to the stored information signals.

Claim 16

The receiver of claim 1 further comprising: control means responsive to the detect signal for enabling said controlling means to enable said counting means for a second integration interval, wherein said controlling means generates an enable signal in response to the detect signal from the second integration interval, and wherein said data clock means is responsive to the enable signal for providing a timing signal at the predetermined baud rate for sampling each symbol, wherein the phase of the timing signal is established in response to the detect signal from the second integration interval.

Claim 17

The receiver of claim 15 wherein the memory means of said analyzing means includes a plurality of threshold tables, each threshold table having a plurality of threshold values, and said receiver further comprises selecting means for selecting one of the plurality of threshold tables, wherein said analyzing means selects the threshold value from the selected threshold table, the threshold value corresponding to the total edge count signal accumulated, and wherein said selecting means selects a second threshold table for the second integration interval.

Claim 18

A radio communications receiver comprising: receiving means for receiving and demodulating a radio frequency signal to generate a received signal; and digital signal absence detecting means coupled to the receiving means for generating an absence signal in response to absence from within the received signal of a signal having a plurality of digital symbols received at a predetermined baud rate, the digital signal absence detecting means comprising: data clock means for generating a timing signal; phase generating means, responsive to the timing signal, for generating a reference signal having a frequency corresponding to the baud rate, the reference signal comprising a plurality of independent phase signals generated relative to the received signal; transition detecting means responsive to the timing signal for detecting transitions which may occur between symbols; counting means responsive to said transition detecting means and said phase generating means, and having a plurality of phase accumulators, each responsive to the detected transitions and one of the phase signals which is selectively coupled thereto for accumulating a transition count when the detected transition coincides with the phase signal selectively coupled thereto; said counting means further including totalizing means for accumulating a total count of the number of transitions detected within a fixed time interval; controlling means for resetting said counting means and for operating said counting means of the fixed time interval and for generating a completion signal at the end of the fixed time interval; and analyzing means, including memory means for storing a table of predetermined threshold values corresponding to the total transitions detected, said analyzing means being coupled to said counting means and responsive to the completion signal, for selecting from said memory means a threshold value corresponding to the total transitions detected, and for generating the absence signal in response to the threshold value selected not being exceeded by a sum of values within any predetermined number of said phase accumulators which correspond to contiguous phases of the reference signal.

Claim 19

A radio communications receiver comprising: receiving means for receiving and demodulating a radio frequency signal to generate a received signal; and digital signal absence detecting means coupled to the receiving means for generating an absence signal in response to absence from within the received signal of a signal having a plurality of digital symbols received at a predetermined baud rate, the digital signal absence detecting means comprising: data clock means for generating a timing signal; phase generating means, responsive to the timing signal, for generating a reference signal having a frequency corresponding to the baud rate, the reference signal comprising a plurality of independent phase signals generated relative to the received signal; transition detecting means responsive to the timing signal for detecting transitions which may occur between symbols; counting means responsive to said transition detecting means and said phase generating means, and having a plurality of phase accumulators, each responsive to the detected transitions and one of the phase signals which is selectively coupled thereto for accumulating a transition count when the detected transition coincides with the phase signal selectively coupled thereto; said counting means further including totalizing means for accumulating a total count of the number of transitions detected within a fixed time interval; controlling means for resetting said counting means and for operating said counting means of the fixed time interval and for generating a completion signal at the end of the fixed time interval; and analyzing means, including memory means for storing a table of predetermined threshold values corresponding to the total transitions detected, said analyzing means being coupled to said counting means and responsive to the completion signal, for selecting from said memory means a threshold value corresponding to the total transitions detected, and for generating the absence signal in response to the threshold value selected not being exceeded by a sum of values within any predetermined number of said phase accumulators which correspond to contiguous phases of the reference signal.

Claim 20

The receiver of claim 17 wherein the receiving means is periodically activated and consumes power while receiving the radio frequency signal, and wherein said receiving means being coupled to said analyzing means for operating in a reduced power mode in response to the absence signal, thereby entering a lower power state.

Claim 23

The method of claim 19 further comprising the step of producing the detect signal in response to the selected threshold value being exceeded by a sum of counts accumulated within a predetermined number of phase accumulators.