US5212442A
Expired / Lapsed
US
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Forced substrate test mode for packaged integrated circuits
Assignee: Micron Technology Inc
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Filing: 1992-03-20
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Granted: 1993-05-18
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Expires: 2012-03-20
Abstract
Abstract An integrated circuit such as an SRAM or DRAM fabricated in a package having a number of external pins includes a plurality of inputs and outputs electrically coupled to the external package pins, an internal substrate that is unconnected to any of the external pins, a test mode indicator circuit having an input coupled to an external pin and an output for providing a test mode signal and a switch responsive to the test mode signal for coupling the substrate to a predetermined voltage. The predetermined voltage can either be ground, or a negative voltage introduced on a pin that is normally set to a logic zero during package level testing. The test mode signal can also be used to disable the on-chip charge pump. The test mode indicator circuit can include a super voltage indicator, an electronic key, or latch circuit in order to receive the test mode indication signal on an existing package pin.
Inventors
- 👤 James E. O'Toole
- 👤 Brian P. Higgins
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 18:17
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/30; G01R31/317; G01R31/31701; G11; G11C; G11C29/00; G11C29/04; G11C29/50; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/41
Claims Analysis
Total Claims: 23
Claim 1
Independent Claim
130 words
An integrated circuit fabricated in a package having a number of external pins, the integrated circuit comprising: a primary circuit having a plurality of inputs and outputs electrically coupled to the external pins; an integrated circuit substrate that is unconnected to any of the external pins; a test mode indicator having an input coupled to an external pin and an output for providing a test mode signal; a charge pump for biasing the substrate to a predetermined voltage in a normal operating mode; and a switch for controlling the substrate voltage in a test mode independently of the operation of the charge pump, the switch having a first node coupled to the substrate, a second node coupled to a voltage source, and an input for receiving the test mode signal.
Claim 2
Dependent Claim
130 words
An integrated circuit fabricated in a package having a number of external pins, the integrated circuit comprising: a primary circuit having a plurality of inputs and outputs electrically coupled to the external pins; an integrated circuit substrate that is unconnected to any of the external pins; a test mode indicator having an input coupled to an external pin and an output for providing a test mode signal; a charge pump for biasing the substrate to a predetermined voltage in a normal operating mode; and a switch for controlling the substrate voltage in a test mode independently of the operation of the charge pump, the switch having a first node coupled to the substrate, a second node coupled to a voltage source, and an input for receiving the test mode signal.
Claim 3
Dependent Claim
22 words
An integrated circuit as in claim 1 further comprising means for disabling the charge pump in response to the test mode signal.
Claim 4
Dependent Claim
18 words
An integrated circuit as in claim 1 in which the test mode indicator comprises a super voltage indicator.
Claim 5
Dependent Claim
18 words
An integrated circuit as in claim 1 in which the test mode indicator comprises an electronic key circuit.
Claim 6
Dependent Claim
20 words
An integrated circuit as in claim 1 further comprising a latch interposed between the test mode indicator and the switch.
Claim 7
Dependent Claim
18 words
An integrated circuit as in claim 1 in which the primary circuit comprises a static random access memory.
Claim 8
Dependent Claim
18 words
An integrated circuit as in claim 1 in which the primary circuit comprises a dynamic random access memory.
Claim 9
Dependent Claim
19 words
An integrated circuit as in claim 1 in which the substrate voltage is substantially equal to the source voltage.
Claim 10
Dependent Claim
25 words
An integrated circuit as in claim 1 in which the switch is coupled to the voltage source at the second node through an external pin.
Claim 11
Dependent Claim
133 words
An integrated circuit fabricated in a package having a number of external pins, the integrated circuit comprising: a primary circuit having a plurality of inputs and outputs electrically coupled to the external pins; an integrated circuit substrate that is unconnected to any of the external pins; a super voltage test mode indicator having an input coupled to an external pin and an output for providing a test mode signal; a charge pump for biasing the substrate to a predetermined voltage in a normal operating mode; and an FET switch for controlling the substrate voltage in a test mode independently of the operation of the charge pump, the switch having a first node coupled to the substrate, a second node coupled to a voltage source, and an input for receiving the test mode signal.
Claim 12
Dependent Claim
133 words
An integrated circuit fabricated in a package having a number of external pins, the integrated circuit comprising: a primary circuit having a plurality of inputs and outputs electrically coupled to the external pins; an integrated circuit substrate that is unconnected to any of the external pins; a super voltage test mode indicator having an input coupled to an external pin and an output for providing a test mode signal; a charge pump for biasing the substrate to a predetermined voltage in a normal operating mode; and an FET switch for controlling the substrate voltage in a test mode independently of the operation of the charge pump, the switch having a first node coupled to the substrate, a second node coupled to a voltage source, and an input for receiving the test mode signal.
Claim 13
Dependent Claim
63 words
An integrated circuit as in claim 10 in which the super voltage test mode indicator comprises: a level shifter having an input coupled to an external pin and an output; and logic means having a first input coupled to the output of the level shifter, a second input for receiving a chip select signal, and an output for providing the test mode signal.
Claim 14
Dependent Claim
108 words
An integrated circuit as in claim 10 in which the logic means comprises: a load coupled between a source of supply voltage and the input of the logic means; an N-channel FET having a drain coupled to the input of the logic means, a gate for receiving the chip select signal, and a source coupled to ground; a delay generator having an input for receiving the chip select signal and an output; and a logic gate having a first input coupled to the input of the logic means, a second input coupled to the output of the delay generator, and an output for providing the test mode signal.
Claim 15
Dependent Claim
24 words
An integrated circuit as in claim 12 in which the load comprises a diode-connected P-channel FET and a diode-connected N-channel FET coupled in series.
Claim 16
Dependent Claim
24 words
An integrated circuit as in claim 12 in which the logic gate comprises a NAND gate having a switching threshold greater than 2.5 volts.
Claim 17
Dependent Claim
60 words
An integrated circuit as in claim 10 in which the FET switch comprises: an inverter having an input for receiving the test mode signal and an output; and an N-channel FET having a gate coupled to the output of the inverter, a drain forming the first node of the switch, and a source forming the second node of the switch.
Claim 18
Dependent Claim
22 words
An integrated circuit as in claim 10 further comprising means for disabling the charge pump in response to the test mode signal.
Claim 19
Dependent Claim
23 words
An integrated circuit as in claim 10 further comprising a latch interposed between the super voltage test mode indicator and the FET switch.
Claim 20
Dependent Claim
18 words
An integrated circuit as in claim 10 in which the primary circuit comprises a static random access memory.
Claim 21
Dependent Claim
18 words
An integrated circuit as in claim 10 in which the primary circuit comprises a dynamic random access memory.
Claim 22
Dependent Claim
19 words
An integrated circuit as in claim 10 in which the substrate voltage is substantially equal to the source voltage.
Claim 23
Dependent Claim
24 words
An integrated circuit as in claim 10 in which the switch is coupled to the source at the second node through an external pin.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-05-17 | 1996-11-16 | 1997-05-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-05-17 | 2000-11-16 | 2001-05-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-05-17 | 2004-11-16 | 2005-05-18 | $7700.00 | Window Closed / Lapsed |