US5224072A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Read-only memory with few programming signal lines
Assignee: Lapis Semiconductor Co Ltd
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Filing: 1991-04-04
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Granted: 1993-06-29
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Expires: 2011-04-04
Abstract
Abstract A signal-generating circuit receives a program signal and generates an output enable signal, a control signal, and a latch signal. In response to the output enable signal, a programmable read-only memory outputs data onto a data bus. In response to the control signal, a three-state buffer outputs data from a first register to the data bus; the data can then be stored in the programmable read-only memory by input of a chip enable signal. In response to the latch signal, a second register latches data output from the programmable read-only memory onto the data bus. An equality checker compares the contents of the first and second registers and generates an equal signal indicating whether they are equal.
Inventors
- 👤 Hiroaki Matsubara
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 19:04
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/22; G11C16/00; G11C16/02; G11C16/06; G11C16/32
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
220 words
A programmable read-only memory circuit comprising: a signal-generating circuit for receiving a program signal and providing, in sequence, a control signal, an output enable signal, and a latch signal; a programmable read-only memory connected to said signal-generating circuit, having an address bus for input of an address and a data bus for input and output of data, for receiving a chip enable signal, storing data present on said data bus at said address responsive to said chip enable signal, and outputting data stored at said address onto said data bus when said output enable signal is active; a counter connected to said address bus, for generating said address; a first register for receiving and holding data to be stored to said programmable read-only memory; a second register, connected to said data bus and said signal-generating circuit, for receiving and holding data present on said data bus when said latch signal becomes active; a three-state buffer, connected to said first register, said data bus, and said signal-generating circuit, for outputting data held in said first register to said data bus when said control signal is active; and an equality checker, connected to said first register and said second register, for comparing contents of said first register and said second register and generating an equal signal indicating whether said contents are equal.
Claim 2
Dependent Claim
220 words
A programmable read-only memory circuit comprising: a signal-generating circuit for receiving a program signal and providing, in sequence, a control signal, an output enable signal, and a latch signal; a programmable read-only memory connected to said signal-generating circuit, having an address bus for input of an address and a data bus for input and output of data, for receiving a chip enable signal, storing data present on said data bus at said address responsive to said chip enable signal, and outputting data stored at said address onto said data bus when said output enable signal is active; a counter connected to said address bus, for generating said address; a first register for receiving and holding data to be stored to said programmable read-only memory; a second register, connected to said data bus and said signal-generating circuit, for receiving and holding data present on said data bus when said latch signal becomes active; a three-state buffer, connected to said first register, said data bus, and said signal-generating circuit, for outputting data held in said first register to said data bus when said control signal is active; and an equality checker, connected to said first register and said second register, for comparing contents of said first register and said second register and generating an equal signal indicating whether said contents are equal.
Claim 3
Dependent Claim
19 words
The circuit of claim 1, wherein said signal-generating circuit deactivates said control signal before activating said output enable signal.
Claim 4
Dependent Claim
38 words
The circuit of claim 1, wherein said circuit is fabricated as part of a semiconductor device and said program input signal, said chip enable signal, and said equal signal are obtained from external terminals of said semiconductor device.
Claim 5
Dependent Claim
39 words
The circuit of claim 1, wherein said first register is a serial-input, parallel-output shift register for receiving said program signal and a serial clock signal, and storing successive bits of said program signal responsive to said serial clock signal.
Claim 6
Dependent Claim
31 words
The circuit of claim 4, wherein said circuit is fabricated as part of a semiconductor device and said serial clock signal is obtained from an external terminal of said semiconductor device.
Claim 7
Dependent Claim
141 words
The circuit of claim 1, wherein said program signal, said control signal, said latch signal, and said output enable signal have a first state and a second state, and: said control signal is active in said first state; said output enable signal is active in said second state; said latch signal is active at transitions from said second state to said first state; when said program signal goes to said first state, said latch signal immediately goes to said first state, said output enable signal goes to said first state after a certain delay, and said control signal goes to said first state after a certain further delay; when said program signal goes to said second state, said control signal immediately goes to said second state, after which said latch signal and said output enable signal go to said second state.
Claim 8
Dependent Claim
133 words
The circuit of claim 6, wherein said signal-generating circuit comprises: a first delay line for receiving said program signal and delaying same by a certain amount; a second delay line for receiving output of said first delay line and delaying same by a certain amount; an AND gate for receiving said program signal and output of said second delay line and performing a logical AND operation thereon, thus generating said control signal; a first OR gate for receiving said program signal and output of said second delay line and performing a logical OR operation thereon, thus generating said latch signal; and a second OR gate for receiving output of said first delay line and output of said second delay line and performing a logical OR operation thereon, thus generating said output enable signal.
Claim 9
Dependent Claim
47 words
The circuit of claim 7, wherein said first delay line and said second delay line comprise, respectively, a first inverter, a second inverter, a third inverter, and a fourth inverter connected in series, input being received at said first inverter and output provided from said fourth inverter.
Claim 10
Dependent Claim
52 words
The circuit of claim 8, wherein said first delay line and said second delay line also comprise, respectively: a first capacitor connected between ground and a point between said first inverter and said second inverter; a second capacitor connected between ground and a point between said second inverter and said third inverter.
References Cited (Backward Citations)
JPS5271154A
Cited
US4410965A
Cited
US4506348A
Cited
US4633441A
Cited
US4628480A
Cited
US4811294A
Cited
US5119330A
Cited
GB2244174A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-06-28 | 1996-12-28 | 1997-06-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-06-28 | 2000-12-28 | 2001-06-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-06-28 | 2004-12-28 | 2005-06-29 | $7700.00 | Window Closed / Lapsed |