Optimized automated macro embedding for standard cell blocks

Claim 2

In a data processing system, a method for automatically arranging the circuits of a circuit array for placement in a semiconductor chip circuit area, the array being built up from a set of circuit elements, having an elemental logic function and a predetermined maximum spatial extent in at least one dimension, that are placed and arranged in a field corresponding to the circuit area, and for automatically embedding a predetermined circuit arrangement having a physical extent in said one dimension larger than the predetermined maximum spatial extent, comprising the steps of; providing a first field filler for the predetermined circuit arrangement, having a spatial extent in said one dimension no larger than the predetermined maximum spatial extent; placing and arranging said circuit elements and said first field filler in said field according to a predetermined algorithm; after arranging the circuit elements, providing at least one further field filler adjacent to said first field filler to define an aggregate field filler having an area substantially the same as the area of the predetermined circuit arrangement; fixing the position in the field of said aggregate field filler so that it cannot be moved in the next step; and then replacing and arranging at least some of said circuit elements in said field to account for said fixed position aggregate field filler.

Claim 3

In a data processing system executing a circuit placement program for a circuit array, the array being built up from a set of circuit elements having an elemental logic function and a predetermined physical size, wherein the circuit elements are placed in a semiconductor chip circuit area by a process of defining, in an area corresponding to the chip circuit area, a field of parallel limit lines having a minimal spacing therebetween determined by the tallest circuit element in the set, and placing and arranging such circuit elements along such limit lines, a method for automatically embedding a predetermined circuit arrangement having a physical height larger than the minimum spacing between the limit lines, comprising the steps of: defining a first field filler for the predetermined circuit arrangement, having a width substantially the same as the width of the arrangement and a height no greater than said minimum spacing between the limit lines; placing and arranging the circuit elements and said first field filer along said limit lines according to a predetermined algorithm; after performing said step of placing and arranging, providing further field fillers to said first field filler to define an aggregate field filler having an area substantially the same as the area of the predetermined circuit arrangement; fixing the position in the field of said aggregate field filler so that it cannot be moved in the next step; and replacing and arranging at least some of the circuit elements along said limit lines to account for said fixed position aggregate field filler.

Claim 4

In a data processing system executing a circuit placement program for a circuit array, the array being built up from a set of circuit elements having an elemental logic function and a predetermined physical size, wherein the circuit elements are placed in a semiconductor chip circuit area by a process of defining, in an area corresponding to the chip circuit area, a field of parallel limit lines having a minimal spacing therebetween determined by the tallest circuit element in the set, and placing and arranging such circuit elements along such limit lines, a method for automatically embedding a predetermined circuit arrangement having a physical height larger than the minimum spacing between the limit lines, comprising the steps of: defining a first field filler for the predetermined circuit arrangement, having a width substantially the same as the width of the arrangement and a height no greater than said minimum spacing between the limit lines; placing and arranging the circuit elements and said first field filer along said limit lines according to a predetermined algorithm; after performing said step of placing and arranging, providing further field fillers to said first field filler to define an aggregate field filler having an area substantially the same as the area of the predetermined circuit arrangement; fixing the position in the field of said aggregate field filler so that it cannot be moved in the next step; and replacing and arranging at least some of the circuit elements along said limit lines to account for said fixed position aggregate field filler.

Claim 5

In a data processing system, a method for automatically arranging the circuits of a circuit array for placement in a semiconductor chip circuit area, the array being built up from a set of circuit elements having an elemental logic function and a predetermined physical size, and for automatically embedding a predetermined circuit arrangement having a physical height larger than the minimum spacing between the limit lines, comprising the steps of; providing, in an area corresponding to the chip circuit area, a field of predefined parallel limit lines having a minimal spacing therebetween determined by the tallest circuit element in the set; providing a first field filler for the predetermined circuit arrangement, having a width substantially the same as the width of the arrangement and a height no greater than said minimum spacing between the limit lines; placing and arranging said circuit elements and said first field filler along said limit lines according to a predetermined algorithm; after arranging the circuit elements and said first field filler, providing further field fillers adjacent to said first field filler to define an aggregate field filler having an area substantially the same as the area of the predetermined circuit arrangement; fixing the position in the field of said aggregate field filler so that it cannot be moved in the next step; then placing and arranging said circuit elements along said limit lines according to said predetermined algorithm; substituting said predetermined circuit arrangement for said aggregate field filler; and placing wires to interconnect said cells and said predetermined circuit arrangement.

Claim 6

In a data processing system, a method for automatically arranging the circuits of a circuit array for placement in a semiconductor chip circuit area, the array being built up from a set of circuit elements having an elemental logic function and a predetermined physical size, and for automatically embedding a predetermined circuit arrangement having a physical height larger than the minimum spacing between the limit lines, comprising the steps of; providing, in an area corresponding to the chip circuit area, a field of predefined parallel limit lines having a minimal spacing therebetween determined by the tallest circuit element in the set; providing a first field filler for the predetermined circuit arrangement, having a width substantially the same as the width of the arrangement and a height no greater than said minimum spacing between the limit lines; placing and arranging said circuit elements and said first field filler along said limit lines according to a predetermined algorithm; after arranging the circuit elements and said first field filler, providing further field fillers adjacent to said first field filler to define an aggregate field filler having an area substantially the same as the area of the predetermined circuit arrangement; fixing the position in the field of said aggregate field filler so that it cannot be moved in the next step; then placing and arranging said circuit elements along said limit lines according to said predetermined algorithm; substituting said predetermined circuit arrangement for said aggregate field filler; and placing wires to interconnect said cells and said predetermined circuit arrangement.

Claim 7

A method according to claim 3 wherein said steps of providing a first field filler and of providing further field fillers are performed by defining said fillers such that their width is greater than that of said circuit arrangement by a predetermined amount to accommodate circuit layout ground rule requirements.

Claim 8

A method according to claim 4 wherein said field is provided with a field coordinate system for characterizing locations therein, said field coordinate system having an axis parallel to said limit lines, and said fillers are each provided with a local coordinate system for characterizing locations therein, said local coordinate system having an axis parallel to said limit lines, wherein said step of defining said fillers comprises the steps of: shifting the start point of the filler in the direction of said axis, within said local coordinate system by a desired amount; and expanding the filler in width by said predetermined amount.

Claim 9

A method according to claim 3 wherein said step of placing said circuit elements along said lines further comprises the step of defining areas within said aggregate field filler within which wiring that connects elements external to the circuit arrangement is permitted to pass.

Claim 10

A method according to claim 6 wherein said step of defining comprises the steps of: identifying available wiring channels within the circuit arrangement; and characterizing said channels with respect to a coordinate system referenced with respect to said field.

Claim 11

A method according to claim 3 further comprising the following steps to be performed after said step of adding further field fillers and before said step of fixing the position of said aggregate field filler: determining whether said aggregate field filler extends beyond the boundaries of said field, and if so, moving said aggregate filler so that it does not so extend.

Claim 12

A method according to claim 8 wherein said step of determining whether said aggregate field filler extends beyond the boundaries comprises the steps of: characterizing the top boundary of said aggregate field filler with respect to a coordinate system referenced to said field, characterizing the top boundary of said field with respect to said coordinate system; and comparing said respective top boundaries so characterized.

Claim 13

A method according to claim 9 wherein said step of moving said aggregate filler so that it does not so extend comprises the steps of: moving, if the result of said step of comparing is that said aggregate filler is outside the boundary of said field, said aggregate field filler origin in a direction perpendicular to said limit lines inward to the next limit line; and repeating the step of characterizing the top boundary of said aggregate field filler, said step of comparing and said step of moving said aggregate field filler origin, until said aggregate field filler is no longer outside the boundary of said field.

Claim 14

A method according to claim 10 wherein: said step of providing limit lines is performed by providing said limit lines such that selected limit lines are spaced apart from an adjacent limit line by a predetermined amount greater than said minimum spacing, which predetermined amount need not be the same for any two such spacings; and said step of providing further field fillers is performed by providing such field fillers having a height corresponding to the combined row spacings which the area of the predetermined circuit arrangement overlaps when its origin is the same as the origin of the first field filler.

Claim 15

A method according to claim 11 wherein said step of providing further field fillers comprises the steps of: determining whether said aggregate field filler extends beyond the top boundary of said field; for the portion of said aggregate field filler so extending, providing further field fillers having a height substantially the same as said minimum spacing; and then moving said aggregate field filler to a position that avoids such extension beyond the top boundary of said field.

Claim 16

A method according to claim 3, wherein the method for embedding a predetermined circuit arrangement includes a method for embedding a plurality of such arrangements, and wherein said step of providing further field fillers comprises the steps of: determining whether any two or more of such aggregate fillers overlap; and if so moving one or more of such aggregate fillers to eliminate such overlap.