US5229331A
Expired / Lapsed
US
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Method to form self-aligned gate structures around cold cathode emitter tips using chemical mechanical polishing technology
Assignee: Micron Technology Inc
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Filing: 1992-02-14
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Granted: 1993-07-20
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Expires: 2012-02-14
Abstract
Abstract A chemical mechanical polishing process for the formation of self-aligned gate structures surrounding an electron emission tip for use in field emission displays in which the emission tip is i) optionally sharpened through oxidation, ii) deposited with a conformal insulating material, iii) deposited with a flowable insulating material, which is reflowed below the level of the tip, iv) optionally deposited with another insulating material, v) deposited with a conductive material layer, and vi) optionally, deposited with a buffering material, vii) planarized with a chemical mechanical planarization (CMP) step, to expose the conformal insulating layer, viii) wet etched to remove the insulating material and thereby expose the emission tip, afterwhich ix) the emitter tip may be coated with a material having a lower work function than silicon.
Inventors
- 👤 Trung T. Doan
- 👤 J. Brett Rolfson
- 👤 Tyler A. Lowrey
- 👤 David A. Cathey
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 01:05
CPC Classifications
H; H01; H01J; H01J9/00; H01J9/02; H01J9/022; H01J9/025; H10; H10P; H10P95/00; H10P95/06; H10P95/062; H01J2201/00; H01J2201/30; H01J2201/304; H01J2201/30403; H01J2201/30426; H01J2201/319; H01J2209/00; H01J2209/02; H01J2209/022; H01J2209/0223; H01J2209/0226
Claims Analysis
Total Claims: 23
Claim 1
Independent Claim
113 words
A process for the formation of self-aligned gate structure around an electron emitting tip, said process comprising the following steps: processing a wafer to form at least one conical cathode on a substrate, said cathode having an emitter tip; depositing at least one conformal gate-to-cathode spacer layer over the tip of said cathode; depositing a flowable insulative layer superjacent said substrate, said insulative layer and said spacer layer establishing a gate-to-substrate spacing layer; depositing a conductive material layer superjacent said gate-to-substrate spacing layer; subjecting the wafer to chemical mechanical planarization (CMP) in order to expose said spacer layer; and removing a portion of said spacer layer surrounding each tip thereby exposing said tip.
Claim 2
Dependent Claim
113 words
A process for the formation of self-aligned gate structure around an electron emitting tip, said process comprising the following steps: processing a wafer to form at least one conical cathode on a substrate, said cathode having an emitter tip; depositing at least one conformal gate-to-cathode spacer layer over the tip of said cathode; depositing a flowable insulative layer superjacent said substrate, said insulative layer and said spacer layer establishing a gate-to-substrate spacing layer; depositing a conductive material layer superjacent said gate-to-substrate spacing layer; subjecting the wafer to chemical mechanical planarization (CMP) in order to expose said spacer layer; and removing a portion of said spacer layer surrounding each tip thereby exposing said tip.
Claim 3
Dependent Claim
20 words
The process according to claim 1, wherein said spacer layer is selectively etchable with respect to said flowable insulative layer.
Claim 4
Dependent Claim
14 words
The process according to claim 2, wherein said conductive material layer comprises doped polysilicon.
Claim 5
Dependent Claim
23 words
The process according to claim 3, wherein the chemical mechanical planarization (CMP) step is performed with an abrasive compound in a polishing slurry.
Claim 6
Dependent Claim
33 words
The process according to claim 4, further comprising the step of depositing a buffering material layer on said conductive material layer prior to subjecting the wafer to the chemical mechanical planarization (CMP) step.
Claim 7
Dependent Claim
23 words
The process according to claim 5, further comprising the step of sharpening said tip by oxidation prior to depositing said gate-to-substrate spacing layer.
Claim 8
Dependent Claim
22 words
The process according to claim 6, wherein said flowable insulative layer comprises at least one of borophosphosilicate glass (BPSG) and spin-on-glass (SOG).
Claim 9
Dependent Claim
13 words
The process according to claim 7, further comprising reflowing said flowable insulative layer.
Claim 10
Dependent Claim
19 words
The process according to claim 8, wherein said flowable insulative layer is reflowed to a level below the tip.
Claim 11
Dependent Claim
22 words
The process according to claim 9, further comprising: depositing said flowable insulative layer on said cathode prior to depositing said spacer layer.
Claim 12
Dependent Claim
22 words
The process according to claim 9, further comprising: depositing said flowable insulative layer on said cathode subsequent to depositing said spacer layer.
Claim 13
Dependent Claim
25 words
The process according to claim 6, wherein said flowable insulative layer comprises at least one of polyimide, a spin on dielectric, and a flowable dielectric.
Claim 14
Dependent Claim
21 words
The process according to claim 10, wherein said cathode is incorporated into an array of like cathodes as an optical display.
Claim 15
Dependent Claim
127 words
A process for the formation of self-aligned low potential anode structures around a cathode tip, said process comprising the following steps: processing a wafer to form at least one conical cathode on a conductive substrate, said cathode having an emitter tip, said cathode having an upper portion and a lower portion; depositing at least one conformal gate-to-cathode spacer layer over said upper portion of said cathode; depositing a flowable insulative layer superjacent said substrate; reflowing said flowable insulative layer below said upper portion of said cathode; depositing a conductive gate layer superjacent said flowable insulative layer; subjecting the wafer to chemical mechanical planarization (CMP) in order to expose said spacer layer; and removing the spacer layer surrounding said upper portion of the cathode thereby exposing the tip.
Claim 16
Dependent Claim
127 words
A process for the formation of self-aligned low potential anode structures around a cathode tip, said process comprising the following steps: processing a wafer to form at least one conical cathode on a conductive substrate, said cathode having an emitter tip, said cathode having an upper portion and a lower portion; depositing at least one conformal gate-to-cathode spacer layer over said upper portion of said cathode; depositing a flowable insulative layer superjacent said substrate; reflowing said flowable insulative layer below said upper portion of said cathode; depositing a conductive gate layer superjacent said flowable insulative layer; subjecting the wafer to chemical mechanical planarization (CMP) in order to expose said spacer layer; and removing the spacer layer surrounding said upper portion of the cathode thereby exposing the tip.
Claim 17
Dependent Claim
22 words
The process according to claim 14, wherein said flowable insulative layer comprises at least one of borophosphosilicate glass (BPSG) and spin-on-glass (SOG).
Claim 18
Dependent Claim
26 words
The process according to claim 15, wherein said spacer layer comprises at least one of Si 3 N 4 , SiO 2 , and silicon oxynitride.
Claim 19
Dependent Claim
22 words
The process according to claim 16, wherein the chemical mechanical planarization step is performed with an abrasive compound in a polishing slurry.
Claim 20
Dependent Claim
16 words
The process according to claim 17, further comprising the step of sharpening the tip by oxidation.
Claim 21
Dependent Claim
33 words
The process according to claim 18, further comprising the step of depositing a buffering material layer on said conductive gate layer prior to subjecting the wafer to the chemical mechanical planarization (CMP) step.
Claim 22
Dependent Claim
99 words
A process for the formation of self-aligned gate structures around an electron emitting cathode tip, said process comprising the following steps: processing a wafer to form at least one cathode having an emitter tip; sharpening the tip of said cathode by oxidation; depositing at least one gate-to-cathode spacer layer over the tip of said cathode; depositing a gate-to-substrate spacer layer; depositing a conductive gate layer; subjecting the wafer to chemical mechanical planarization (CMP)to expose said gate-to-cathode spacer; removing said gate-to-cathode spacer layer over the tip; and coating the cathode with a material having a lower work function than silicon.
Claim 23
Dependent Claim
99 words
A process for the formation of self-aligned gate structures around an electron emitting cathode tip, said process comprising the following steps: processing a wafer to form at least one cathode having an emitter tip; sharpening the tip of said cathode by oxidation; depositing at least one gate-to-cathode spacer layer over the tip of said cathode; depositing a gate-to-substrate spacer layer; depositing a conductive gate layer; subjecting the wafer to chemical mechanical planarization (CMP)to expose said gate-to-cathode spacer; removing said gate-to-cathode spacer layer over the tip; and coating the cathode with a material having a lower work function than silicon.
References Cited (Backward Citations)
US3755704A
Cited
US3665241A
Cited
US3812559A
Cited
US3875442A
Cited
US3998678A
Cited
US3970887A
Cited
US3921022A
Cited
JPS56160740A
Cited
US4666553A
Cited
US4746629A
Cited
US4943343A
Cited
US5143820A
Cited
US5036015A
Cited
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