Nonvolatile semiconductor memory wherein dummy cells are used for generating a potential for detecting data

Claim 2

A nonvolatile semiconductor memory comprising: a first precharge-discharge type memory circuit having a first plurality of bit lines, a first plurality of non-volatile memory cells and at least one nonvolatile dummy cell connected to said first plurality of bit lies; a second precharge-discharge type memory circuit having a second plurality of bit lines and a second plurality of nonvolatile memory cells and at least one nonvolatile dummy cell connected to the second plurality of bit lines of the second memory circuit; cell-selecting means for selecting one of the first plurality of nonvolatile memory cells of the first memory circuit, along with one of the at least one dummy cell of the second memory circuit, or one of the second plurality of memory cells of the second memory circuit, along with one of the at least one dummy cell of the first memory circuit; data-detecting means for comparing a potential output from the first or second memory circuit including the selected memory cell, respectively with a potential output from the first or second memory circuit including the dummy cell which has been selected by the cell-selecting means, thereby to detect data stored in the selected memory cell; first and second bit-line selecting circuits included in the cell selecting means, each comprising a plurality of bit-line selecting transistors connected, at a first end, to said bit lines in each memory circuit, respectively, and connected to one another at a second end in each memory circuit, thus forming a node in each memory circuit, and a column decoder for receiving the column-address signals and for selecting and driving one of said bit-line selecting transistors in accordance with the column-address signals; a plurality of level-shifting transistors each connected at a first end to the node at the second ends of said plurality of bit-line selecting transistors for each memory circuit; and a plurality of precharge transistors each respectively connected at a first end to a second end of each of said plurality of level-shifting transistors.

Claim 3

A nonvolatile semiconductor memory comprising; a first precharge-discharge type memory circuit having a first plurality of bit liens, a first plurality of nonvolatile memory cells and a first at least one nonvolatile dummy cell connected to the first plurality of bit lines, said first at least one dummy cell having an electrical characteristic different from that of the first plurality nonvolatile memory cells, a first plurality of word lines for selecting the first plurality nonvolatile memory cells, and a dummy word line for simultaneously selecting the first at least one nonvolatile dummy cell connected to said first plurality of bit lines, respectively; a second precharge-discharge type memory circuit having a second plurality of bit lines, a second plurality of nonvolatile memory cells and a second at least one nonvolatile dummy cell connected to the second plurality of bit lines, said second at least one dummy cell having an electrical characteristic different from that of the second plurality of nonvolatile memory cells, a second plurality of word lines for selecting the second plurality of nonvolatile memory cells, and a dummy word line for simultaneously selecting the second at least one nonvolatile dummy cell connected to said second plurality of bit lines, respectively; cell-selecting means for selecting one of the first plurality of nonvolatile emory cells of the first memory circuit, along with the second at least one nonvolatile dummy cell of the second memory circuit, or one of the second plurality of nonvolatile memory cells of the second memory circuit, along with the first at least one nonvolatile dummy cell of the first memory circuit, thereby to read data from the selected nonvolatile memory cell; data-detecting means for comparing a potential output from the first or second memory circuit including the nonvolatile memory cell which has been selected by the cell-selecting means, respectively with a potential output from the first or second memory circuit including the nonvolatile dummy cell which has been selected by the cell-selecting means, thereby to detect data stored in the selected nonvolatile memory cell; first and second bit-line selecting circuits included in the cell selecting means, each comprising a plurality of bit-line selecting transistors connected, at a first end, to said bit lines in each memory circuit, respectively, and connected to each other at a second end in each memory circuit, thus forming a node in each memory circuit, and a column decoder for receiving the column-address signals and for selecting and driving one of said bit-line selecting transistors in accordance with the column-address signals; a plurality of level-shifting transistors each connected, at a first end to the node at the second ends of said bit-line selecting transistors for each memory circuit; and a plurality of precharge transistors each connected, at a first end, to a second end of each of said plurality of level-shifting transistors.

Claim 4

A nonvolatile semiconductor memory comprising; a first precharge-discharge type memory circuit having a first plurality of bit liens, a first plurality of nonvolatile memory cells and a first at least one nonvolatile dummy cell connected to the first plurality of bit lines, said first at least one dummy cell having an electrical characteristic different from that of the first plurality nonvolatile memory cells, a first plurality of word lines for selecting the first plurality nonvolatile memory cells, and a dummy word line for simultaneously selecting the first at least one nonvolatile dummy cell connected to said first plurality of bit lines, respectively; a second precharge-discharge type memory circuit having a second plurality of bit lines, a second plurality of nonvolatile memory cells and a second at least one nonvolatile dummy cell connected to the second plurality of bit lines, said second at least one dummy cell having an electrical characteristic different from that of the second plurality of nonvolatile memory cells, a second plurality of word lines for selecting the second plurality of nonvolatile memory cells, and a dummy word line for simultaneously selecting the second at least one nonvolatile dummy cell connected to said second plurality of bit lines, respectively; cell-selecting means for selecting one of the first plurality of nonvolatile emory cells of the first memory circuit, along with the second at least one nonvolatile dummy cell of the second memory circuit, or one of the second plurality of nonvolatile memory cells of the second memory circuit, along with the first at least one nonvolatile dummy cell of the first memory circuit, thereby to read data from the selected nonvolatile memory cell; data-detecting means for comparing a potential output from the first or second memory circuit including the nonvolatile memory cell which has been selected by the cell-selecting means, respectively with a potential output from the first or second memory circuit including the nonvolatile dummy cell which has been selected by the cell-selecting means, thereby to detect data stored in the selected nonvolatile memory cell; first and second bit-line selecting circuits included in the cell selecting means, each comprising a plurality of bit-line selecting transistors connected, at a first end, to said bit lines in each memory circuit, respectively, and connected to each other at a second end in each memory circuit, thus forming a node in each memory circuit, and a column decoder for receiving the column-address signals and for selecting and driving one of said bit-line selecting transistors in accordance with the column-address signals; a plurality of level-shifting transistors each connected, at a first end to the node at the second ends of said bit-line selecting transistors for each memory circuit; and a plurality of precharge transistors each connected, at a first end, to a second end of each of said plurality of level-shifting transistors.