US5233206A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Double digitlines for multiple programming of prom applications and other anti-fuse circuit element applications
Assignee: Micron Technology Inc
•
Filing: 1991-11-13
•
Granted: 1993-08-03
•
Expires: 2011-11-13
Abstract
Abstract The present invention provides a programmable structure for programmable integrated circuits, such as programmable read-only memory (PROM) which utilizes one-sided ozone spacers constructed on the digitlines as well as on the wordlines thereby providing two, one time programmable nodes at each digit/word/digit' intersection. An oxide/nitride/oxide layer (ONO) is used as an interface between underlying parallel rows of digit lines, having one-sided ozone spacers, and overlying parallel columns of word lines, also having one-sided ozone spacers, and further overlying parallel rows' of digitlines' in a programmable read only memory. With a lower level of digitlines passing under a middle level of wordlines and an upper level of digitlines' passing over the middle level of wordlines, a row/column/digit' matrix is formed thereby providing a programmable row/column/row' matrix in a memory array. Each crossing point of the digit/word lines and the word/digit' lines in the matrix will be permanently programmed to either a one or a zero by rupturing the thin ONO dielectric interface by applying the appropriate voltage potential between the associated digit/word/digit' line conductors.
Inventors
- 👤 Roger R. Lee
- 👤 Tyler A. Lowrey
- 👤 D. Mark Durcan
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 11:01
CPC Classifications
G; G11; G11C; G11C17/00; G11C17/14; G11C17/16; H; H10; H10B; H10B20/00; H10B20/20; H10W; H10W20/00; H10W20/40; H10W20/49; H10W20/491
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
237 words
A programmable structure having first and second one-time programmable nodes in an integrated circuit comprising: a) a patterned first conductor having an overlying patterned first dielectric; b) a second dielectric adjacent the patterned sides of said first conductor and said first dielectric, said second dielectric being a first thick dielectric spacer on a first patterned side of said first conductor and said first dielectric; c) a third dielectric layer blanketing said first thick dielectric spacer, said first dielectric and a second patterned side of said first conductor and said first dielectric; d) a patterned second conductor overlying said first conductor, said second conductor having an overlying patterned fourth dielectric residing in intersecting angular fashion to said first conductor with said third dielectric being a first programmable interface therebetween, thereby forming said first programmable node; e) a fifth dielectric adjacent the patterned sides of said fifth conductor and said fourth dielectric, said second dielectric being a second thick dielectric spacer on a first patterned side of said second conductor and said fourth dielectric; f) a sixth dielectric ;layer blanketing said second thick dielectric spacer, said fourth dielectric and a second patterned side of said second conductor and said fifth dielectric; and g) a patterned third conductor overlying said second patterned conductor, said third conductor residing in intersecting angular fashion to said second conductor with said sixth dielectric being a second interface therebetween, thereby forming said second programmable node.
Claim 2
Dependent Claim
237 words
A programmable structure having first and second one-time programmable nodes in an integrated circuit comprising: a) a patterned first conductor having an overlying patterned first dielectric; b) a second dielectric adjacent the patterned sides of said first conductor and said first dielectric, said second dielectric being a first thick dielectric spacer on a first patterned side of said first conductor and said first dielectric; c) a third dielectric layer blanketing said first thick dielectric spacer, said first dielectric and a second patterned side of said first conductor and said first dielectric; d) a patterned second conductor overlying said first conductor, said second conductor having an overlying patterned fourth dielectric residing in intersecting angular fashion to said first conductor with said third dielectric being a first programmable interface therebetween, thereby forming said first programmable node; e) a fifth dielectric adjacent the patterned sides of said fifth conductor and said fourth dielectric, said second dielectric being a second thick dielectric spacer on a first patterned side of said second conductor and said fourth dielectric; f) a sixth dielectric ;layer blanketing said second thick dielectric spacer, said fourth dielectric and a second patterned side of said second conductor and said fifth dielectric; and g) a patterned third conductor overlying said second patterned conductor, said third conductor residing in intersecting angular fashion to said second conductor with said sixth dielectric being a second interface therebetween, thereby forming said second programmable node.
Claim 3
Dependent Claim
68 words
The programmable structure of claim 1 wherein said first programmable node is programmed by rupturing said third dielectric by applying a voltage potential between said first and said second conductors thereby producing an intercoupling pn junction therebetween and said second programmable node is programmed by rupturing said sixth dielectric by applying a voltage potential between said second and said third conductors thereby producing an intercoupling pn junction therebetween.
Claim 4
Dependent Claim
14 words
The programmable structure of claim 1 wherein said integrated circuit comprises a memory device.
Claim 5
Dependent Claim
16 words
The integrated circuit of claim 3 wherein said memory device comprises a programmable read only memory.
Claim 6
Dependent Claim
15 words
The integrated circuit of claim 3 wherein said memory device comprises a programmable logic array.
Claim 7
Dependent Claim
14 words
The integrated circuit of claim 3 wherein said memory device comprises programmable array logic.
Claim 8
Dependent Claim
17 words
The integrated circuit of claim 1 wherein said programmable structure is formed on a substrate comprising silicon.
Claim 9
Dependent Claim
17 words
The integrated circuit of claim 1 wherein said first, second, fourth and fifth dielectric layers comprise oxide.
Claim 10
Dependent Claim
15 words
The integrated circuit of claim 1 wherein said third and sixth dielectric layers comprise oxide/nitride/oxide.
Claim 11
Dependent Claim
15 words
The programmable structure of claim 1 wherein said second and fifth dielectric spacers comprise ozone.
Claim 12
Dependent Claim
16 words
The integrated circuit of claim 1 wherein said first, second and third conductors comprise doped polysilicon.
Claim 13
Dependent Claim
31 words
The integrated circuit of claim 11 wherein said said first and third polysilicon conductor doping is to an n-type conductivity and said second polysilicon conductor doping is to a p-type conductivity.
Claim 14
Dependent Claim
31 words
The integrated circuit of claim 11 wherein said said first and third polysilicon conductor doping is to a p-type conductivity and said second polysilicon conductor doping is to an n-type conductivity.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-08-02 | 1997-02-01 | 1997-08-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-08-02 | 2001-02-01 | 2001-08-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-08-02 | 2005-02-01 | 2005-08-03 | $7700.00 | Window Closed / Lapsed |