Filter with hysteresis for trip point applications

Claim 2

A circuit for processing a measurement signal responsive to a sender for measuring a vehicle parameter, comprising: means for providing first and second reference signals alternately selected in response to a control signal, the first reference signal selected if the control signal is a first signal condition and the second reference signal selected if the control signal is a second signal condition, the first reference signal being above the second reference signal; means for comparing the measurement signal to the selected reference signal and providing a comparison output signal therefrom; means for filtering the comparison output signal, including an up/down counter having overflow and underflow outputs providing overflow and underflow output signals as a filtered response to the comparison output signal; means for providing the control signal in response to the overflow and underflow output signals, the control signal comprising the first signal condition if the measurement signal is below the selected reference signal for a predetermined number of clock pulses and the control signal comprising the second signal condition if the measurement signal is above the selected reference signal for a predetermined number of clock pulses, whereby the control signal is filtered and has hysteresis minimizing repeated switching of the control signal between the first and second signal conditions when the parameter measurement is near a selected reference level; means for alerting an operator in response to the control signal.

Claim 3

The circuit of claim 1 wherein the means for alerting the operator in response to the control signal includes a telltale which emits light in response to only one of the two conditions of the control signal.

Claim 4

The circuit of claim 1 wherein the means for alerting the operator in response to the control signal includes an air core gauge, responsive to one of the two conditions of the control signal.

Claim 5

The circuit of claim 1 wherein the reference signal means comprises: a resistor chain, coupled between a vehicle ignition voltage and ground and having a set of taps, each tap at a junction between two resistors in the resistor chain, wherein a first tap of the set of taps provides the first reference signal and a second tap of the set of taps provides the second reference signal; and a multiplexer having a select input coupled to the control signal means, reference inputs coupled to the first and second taps, and an output coupled to the comparison means.

Claim 6

The circuit of claim 1 wherein the reference signal means comprises: a resistor chain, coupled between a vehicle ignition voltage and ground and having a set of taps, each tap at a junction between two resistors in the resistor chain, wherein a first tap of the set of taps provides the first reference signal and a second tap of the set of taps provides the second reference signal; and a memory unit having an address input coupled to the control signal means and a data output selecting the first and second reference signals in response to the control signal.

Claim 7

The circuit of claim 1 wherein the comparing means comprises a comparator with two inputs, one of the comparator inputs being an inverting input and the other a non-inverting input, wherein one of the comparator inputs is coupled to the measurement signal, the other comparator input is coupled to the selected reference signal, and an output of the comparator provides the comparison output signal.

Claim 8

The circuit of claim 1 wherein the filtering means comprises: a clock circuit providing clock pulses on a clock line; and wherein the up/down counter includes a clock input coupled to the clock line, a select input receiving the comparison output signal, and underflow and overflow outputs, wherein in response to a first state of the comparison output signal, the up/down counter counts in a first direction and in response to a second state of the comparison output signal the up/down counter counts in a second direction.

Claim 9

The circuit of claim 7 wherein the control signal means comprises a flip flop having two inputs, a set input and a preset input, one of the two inputs coupled to the overflow output of the up/down counter and the other of the two inputs coupled to the underflow output of the up/down counter, the flip flop also having an output which outputs the control signal, the control signal being the first signal condition when one of the flip flop inputs receives a high level signal and the control signal being the second signal condition when the other of the flip flop inputs receives a high level signal.

Claim 10

The circuit of claim 8 wherein the clock circuit comprises an oscillator and a divider circuit, the divider circuit having successive frequency dividers connected in series and a first frequency divider in the series receiving pulses from the oscillator, wherein each frequency divider has an output providing a signal with a clock frequency one half the clock frequency the preceding frequency divider, and wherein the clock line is coupled to one of the divider outputs.

Claim 11

The circuit of claim 9 wherein the clock line is coupled to one of the divider outputs with a metal mask in an integrated circuit package.

Claim 12

The circuit of claim 1 wherein the reference signal means, comparing means, filtering means, and control signal means are all fabricated onto a single integrated circuit.

Claim 13

The circuit of claim 1 also comprising a stabilization means for disabling the filter means for a predetermined period of time after the control signal achieves the first signal condition.

Claim 14

The circuit of claim 1 also comprising a stabilization means for disabling the filter means for a predetermined period of time after the control signal achieves the second signal condition.

Claim 15

The circuit of claim 1 also comprising means, coupled between the control signal means and the comparing means, for providing flashing operation of the alerting means.

Claim 16

The circuit of claim 1 wherein the reference signal means comprises: a resistor chain, coupled between a vehicle ignition voltage and ground and having a set of taps, each tap at a junction between two resistors in the resistor chain, wherein a first tap of the set of taps provides the first reference signal and a second tap of the set of taps provides the second reference signal; a memory unit having an address input coupled to the control signal means and a data output coupled to a decoder; the decoder output coupled to a set of transmission gates, each transmission gate coupled to one tap of the set of taps and to the comparing means, selecting the first and second reference signals in response to the data output of the memory unit.

Claim 17

A circuit for processing a measurement signal indicative of a vehicle parameter, indicating if the vehicle parameter is below a first desired level or above a second desired level, comprising: means for providing first and second reference signals alternately selected in response to a control signal, the first reference signal selected if the control signal is a first signal condition and the second reference signal selected if the control signal is a second signal condition, the first reference signal being above the second reference signal; means for providing third and fourth reference signals alternately selected in response to the control signal, the fourth reference signal selected if the control signal is the first signal condition and the third reference signal selected if the control signal is the second signal condition, the third reference signal being above the fourth reference signal, the first and second reference signals being above the third reference signal; means for comparing the measurement signal to the selected reference signals and for providing a comparison output signal therefrom, wherein (i) if the first and fourth reference signals are selected, the comparison output signal has a first state if the measurement signal is below the first reference signal and above the fourth reference signal and a second state if the measurement signal is above the first reference signal or below the fourth reference signal, and (ii) if the second and third reference signals are selected, the comparison output signal has the first state if the measurement signal is below the second reference signal and above the third reference signal and the second state if the measurement signal is above the second reference signal or below the third reference signal; means for filtering the comparison output signal, including an up/down counter having overflow and underflow outputs providing overflow and underflow output signals as a filtered response to the comparison signal; means for providing the control signal in response to the overflow and underflow output signals, the control signal comprising the first signal condition if the comparison output signal has the second state for a predetermined number of clock pulses and the control signal comprising the second signal condition if the comparison output signal has the first state for a predetermined number of clock pulses, whereby the control signal is filtered and has hysteresis minimizing repeated switching of the control signal between the first and second signal conditions when the measurement signal is near one of the selected reference levels; means for alerting an operator in response to the control signal.

Claim 18

A circuit for processing a measurement signal indicative of a vehicle parameter, indicating if the vehicle parameter is below a first desired level or above a second desired level, comprising: means for providing first and second reference signals alternately selected in response to a control signal, the first reference signal selected if the control signal is a first signal condition and the second reference signal selected if the control signal is a second signal condition, the first reference signal being above the second reference signal; means for providing third and fourth reference signals alternately selected in response to the control signal, the fourth reference signal selected if the control signal is the first signal condition and the third reference signal selected if the control signal is the second signal condition, the third reference signal being above the fourth reference signal, the first and second reference signals being above the third reference signal; means for comparing the measurement signal to the selected reference signals and for providing a comparison output signal therefrom, wherein (i) if the first and fourth reference signals are selected, the comparison output signal has a first state if the measurement signal is below the first reference signal and above the fourth reference signal and a second state if the measurement signal is above the first reference signal or below the fourth reference signal, and (ii) if the second and third reference signals are selected, the comparison output signal has the first state if the measurement signal is below the second reference signal and above the third reference signal and the second state if the measurement signal is above the second reference signal or below the third reference signal; means for filtering the comparison output signal, including an up/down counter having overflow and underflow outputs providing overflow and underflow output signals as a filtered response to the comparison signal; means for providing the control signal in response to the overflow and underflow output signals, the control signal comprising the first signal condition if the comparison output signal has the second state for a predetermined number of clock pulses and the control signal comprising the second signal condition if the comparison output signal has the first state for a predetermined number of clock pulses, whereby the control signal is filtered and has hysteresis minimizing repeated switching of the control signal between the first and second signal conditions when the measurement signal is near one of the selected reference levels; means for alerting an operator in response to the control signal.

Claim 19

The circuit of claim 16 wherein the reference signal means comprise: a resistor chain, coupled between a regulated voltage supply and a ground, and having a set of taps, each tap at a junction between two resistors in the resistor chain, wherein a first tap of the set of taps provides the first reference signal, a second tap of the set of taps provides the second reference signal, a third tap of the set of taps provides the third reference signal and the fourth tap of the set of taps provides the fourth reference signal; a first multiplexer having a select input coupled to the control signal means, reference inputs coupled to the first and second taps, and an output coupled to the comparison means; and a second multiplexer having a select input coupled to the control signal means, reference inputs coupled to the third and fourth taps, and an output coupled to the comparison means.

Claim 20

The circuit of claim 16, wherein the comparing means comprises: a first comparator, with an inverting input and a non-inverting input wherein the non-inverting input is coupled to the measurement signal and the inverting input is coupled to either the first or the second reference signal, whichever is selected; a second comparator, with an inverting input and a non-inverting input wherein the inverting input is coupled to the measurement signal and the non-inverting input is coupled to either the third or fourth reference signal, whichever is selected; an OR gate with two inputs and an output, the two inputs coupled to outputs of the first and second comparators, wherein the output of the OR gate is the comparison output signal.

Claim 21

The circuit of claim 16 wherein the filtering means comprises: a clock circuit providing clock pulses on a clock line; and wherein the up/down counter includes a clock input coupled to the clock line, a select input receiving the comparison output signal, and underflow and overflow outputs, wherein in response to a first state of the comparison output signal, the up/down counter counts in a first direction and in response to a second state of the comparison output signal the up/down counter counts in a second direction.

Claim 22

The circuit of claim 19 wherein the control signal means comprises a flip flop having two inputs, a set input and a preset input, one of the two inputs coupled to the overflow output of the up/down counter and the other of the two inputs coupled to the underflow output of the up/down counter, the flip flop also having an output which outputs the control signal, the control signal being the first signal condition when one of the flip flop inputs receives a high level signal and the control signal being the second signal condition when the other of the flip flop inputs receives a high level signal.

Claim 23

The circuit of claim 19 wherein the clock circuit comprises an oscillator and a divider circuit, the divider circuit having successive frequency dividers connected in series and a first frequency divider in the series receiving pulses from the oscillator, wherein each frequency divider has an output providing a signal with a clock frequency one half the clock frequency the preceding frequency divider, and wherein the clock line is coupled to one of the divider outputs.

Claim 24

The circuit of claim 21 wherein the clock line is coupled to one of the divider outputs with a metal mask in an integrated circuit package.

Claim 25

The circuit of claim 16 wherein the first and second reference signal means, comparing means, filtering means, and control signal means are all fabricated onto a single integrated circuit.

Claim 26

The circuit of claim 16 also comprising a stabilization means for disabling the filter means for a predetermined period of time after the control signal achieves the first signal condition.

Claim 27

The circuit of claim 16 also comprising a stabilization means for disabling the filter means for a predetermined period of time after the control signal achieves the second signal condition.

Claim 28

The circuit of claim 16 also comprising feedback means, coupled between the control signal means and the comparing means, for providing flashing operation of the altering means.

Claim 29

The circuit of claim 16 wherein the alerting means includes a telltale which emits light in response to only one of the two control signal conditions.

Claim 30

The circuit of claim 16 wherein the alerting means includes an air core gauge responsive to one of the two control signal conditions.

Claim 33

The apparatus of claim 29 wherein the first and second reference signals are determined through IC mask options.

Claim 34

The apparatus of claim 29 wherein the first and second reference signals are programmable.

Claim 37

The apparatus of claim 32 wherein the first, second, third and fourth reference signals are determined through IC mask options.

Claim 38

The apparatus of claim 32 wherein the first, second, third and fourth reference signals are programmable.

Claim 39

An integrated circuit apparatus for processing a set of measurement signals responsive to a set of senders, comprising: means for providing a set of reference signals, the set of reference signals comprising subsets of first and second reference signals, each subset corresponding to one of the measurement signals; memory means for addressably storing information, including an address input and a data output, wherein each reference signal of the set of reference signals corresponds to one address of a set of addresses in the memory means; counter means for selectively addressing the memory means, thereby selecting one of the subsets of reference signals; a set of filter means for filtering data, each filter means corresponding to one measurement of the set of measurement signals and one subset of reference signals, comprising: (i) means for addressing the memory means in response to a control signal to select the corresponding first or second reference signal; (ii) means for comparing a corresponding measurement signal to the selected reference signal and for providing a comparison output signal therefrom; (iii) means for filtering the comparison output signal, including an up/down counter having overflow and underflow outputs providing overflow and underflow output signals as a filtered response to the comparison output signal; (iv) means for providing the control signal in response to the overflow and underflow output signals, the control signal comprising a first signal condition fi the corresponding output signal is below the selected reference signal for a predetermined number of clock pulses and the control signal comprising a second signal condition if the corresponding output signal is above the selected reference signal for a predetermined number of clock pulses; wherein the counter means selectively activates each of the filter means so that only one filter means is activated at one time and the counter means selects the corresponding subset of first and second reference signals for each filter means, and wherein, the memory means is addressed in response to the control signal, thereby selecting the first or second reference signals.

Claim 40

An integrated circuit apparatus for processing a set of measurement signals responsive to a set of senders, comprising: means for providing a set of reference signals, the set of reference signals comprising subsets of first and second reference signals, each subset corresponding to one of the measurement signals; memory means for addressably storing information, including an address input and a data output, wherein each reference signal of the set of reference signals corresponds to one address of a set of addresses in the memory means; counter means for selectively addressing the memory means, thereby selecting one of the subsets of reference signals; a set of filter means for filtering data, each filter means corresponding to one measurement of the set of measurement signals and one subset of reference signals, comprising: (i) means for addressing the memory means in response to a control signal to select the corresponding first or second reference signal; (ii) means for comparing a corresponding measurement signal to the selected reference signal and for providing a comparison output signal therefrom; (iii) means for filtering the comparison output signal, including an up/down counter having overflow and underflow outputs providing overflow and underflow output signals as a filtered response to the comparison output signal; (iv) means for providing the control signal in response to the overflow and underflow output signals, the control signal comprising a first signal condition fi the corresponding output signal is below the selected reference signal for a predetermined number of clock pulses and the control signal comprising a second signal condition if the corresponding output signal is above the selected reference signal for a predetermined number of clock pulses; wherein the counter means selectively activates each of the filter means so that only one filter means is activated at one time and the counter means selects the corresponding subset of first and second reference signals for each filter means, and wherein, the memory means is addressed in response to the control signal, thereby selecting the first or second reference signals.

Claim 41

The apparatus of claim 35 wherein the set of filter means comprises four filter means.

Claim 42

The apparatus of claim 35 wherein the set of filter means comprises at least one filter means, the set of measurement signals comprises at least one measurement signal, and the set of reference signals comprises at least one subset of first and second reference signals.