US5237530A
Expired / Lapsed
US
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Frasable non-volatile semiconductor memory device having read/write test function
Assignee: Fujitsu Ltd
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Filing: 1991-11-20
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Granted: 1993-08-17
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Expires: 2011-11-20
Abstract
Abstract An erasable non-volatile semiconductor memory device has a plurality of erasable non-volatile memory cells each comprising two cell transistors, the write statuses of which are inverted, and detects the write status of each memory cell by a differential type detection circuit through first and second bit lines connected to the two cell transistors. Further, the erasable non-volatile semiconductor memory device sets all cell transistors constructing a plurality of the memory cells to the erasing status or write status in entirety, and controls the connection of the first and second bit lines for executing the read/write test. Therefore, the erasable non-volatile semiconductor memory device according to the present invention can reduce the erasing process cycles, which requires a long time, falsely read out the "0" data and "1" data without writing actual data into each memory cell to shorten the test time, and thus can supply a low price product.
Inventors
- 👤 Nobuaki Takashina
- 👤 Takao Akaogi
- 👤 Masanobu Yoshida
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 09:02
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/04; G11C29/08; G11C29/12; G11C29/18; G11C29/30; G11C29/34; G11C29/52
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
312 words
An erasable non-volatile semiconductor memory device having a plurality of erasable non-volatile memory cells each comprising two cell transistors, the write statuses of which are inverted, and detecting the write status of each of said memory cells by a differential type detection circuit through first and second bit lines connected respectively to said two cell transistors of said memory cell, to thereby read out the contents of said memory cell, wherein said erasable non-volatile semiconductor memory device comprises: an all cell transistor erasion means for erasing all of said cell transistors constituting a plurality of said memory cells; a first test means for cutting off said first bit line connected to one of said cell transistors from said differential type detection circuit, and for connecting said second bit line connected to the other of said cell transistors of said memory cell to said differential type detection circuit to carry out a test of a first write level; a second test means for cutting off said second bit line from said differential type detection circuit, and for connecting said first bit line to said differential type detection circuit to carry out a test of a second write level; an all cell transistor write means for writing all of said cell transistors constituting a plurality of said memory cells; a third test means for connecting said second bit line to the ground, and for connecting said first bit line to the ground, and for connecting said first bit line to said differential type detection circuit to carry out a test of the first write level; and a fourth test means for connecting said first bit line to the ground, and for connecting said second bit line to said differential type detection circuit to carry out a test of the second write level, to thereby execute a read/write test of all of said memory cells.
Claim 2
Dependent Claim
312 words
An erasable non-volatile semiconductor memory device having a plurality of erasable non-volatile memory cells each comprising two cell transistors, the write statuses of which are inverted, and detecting the write status of each of said memory cells by a differential type detection circuit through first and second bit lines connected respectively to said two cell transistors of said memory cell, to thereby read out the contents of said memory cell, wherein said erasable non-volatile semiconductor memory device comprises: an all cell transistor erasion means for erasing all of said cell transistors constituting a plurality of said memory cells; a first test means for cutting off said first bit line connected to one of said cell transistors from said differential type detection circuit, and for connecting said second bit line connected to the other of said cell transistors of said memory cell to said differential type detection circuit to carry out a test of a first write level; a second test means for cutting off said second bit line from said differential type detection circuit, and for connecting said first bit line to said differential type detection circuit to carry out a test of a second write level; an all cell transistor write means for writing all of said cell transistors constituting a plurality of said memory cells; a third test means for connecting said second bit line to the ground, and for connecting said first bit line to the ground, and for connecting said first bit line to said differential type detection circuit to carry out a test of the first write level; and a fourth test means for connecting said first bit line to the ground, and for connecting said second bit line to said differential type detection circuit to carry out a test of the second write level, to thereby execute a read/write test of all of said memory cells.
Claim 3
Dependent Claim
25 words
An erasable non-volatile semiconductor memory device as claimed in claim 1, wherein said cell transistors are constituted by floating gate avalanche injection MIS (FAMIS) transistors.
Claim 4
Dependent Claim
59 words
An erasable non-volatile semiconductor memory device as claimed in claim 1, wherein the cutting-off process of either said first bit line or said second bit line is carried out by the switching elements provided between each of two cell transistors of said memory cell and said differential type detection circuit and controlled during a test of said memory cells.
Claim 5
Dependent Claim
242 words
An erasable non-volatile semiconductor memory device, having a plurality of erasable non-volatile memory cells each comprising two cell transistors, the write statuses of which are inverted, and detecting the write status of each of said memory cells by a differential type detection circuit through first and second bit lines connected respectively to said two cell transistors of said memory cell, to thereby read out the contents of said memory cell, wherein said erasable non-volatile semiconductor memory device comprises: an all cell transistor erasion means for erasing all of said cell transistors constituting a plurality of said memory cells; a first test means for connecting said first bit line connected to one of said cell transistors to a power supply means to carry out a test of a first write level; a second test means for connecting said second bit line connected to the other of said cell transistors to said power supply means to carry out a test of a second write level; an all cell transistor write means for writing all of said cell transistors constituting a plurality of said memory cells; a third test means for connecting said second bit line to the ground to carry out a test of the first write level; and a fourth test means for connecting said first bit line to the ground to carry out a test of the second write level, to thereby execute a read/write test of all of said memory cells.
Claim 6
Dependent Claim
242 words
An erasable non-volatile semiconductor memory device, having a plurality of erasable non-volatile memory cells each comprising two cell transistors, the write statuses of which are inverted, and detecting the write status of each of said memory cells by a differential type detection circuit through first and second bit lines connected respectively to said two cell transistors of said memory cell, to thereby read out the contents of said memory cell, wherein said erasable non-volatile semiconductor memory device comprises: an all cell transistor erasion means for erasing all of said cell transistors constituting a plurality of said memory cells; a first test means for connecting said first bit line connected to one of said cell transistors to a power supply means to carry out a test of a first write level; a second test means for connecting said second bit line connected to the other of said cell transistors to said power supply means to carry out a test of a second write level; an all cell transistor write means for writing all of said cell transistors constituting a plurality of said memory cells; a third test means for connecting said second bit line to the ground to carry out a test of the first write level; and a fourth test means for connecting said first bit line to the ground to carry out a test of the second write level, to thereby execute a read/write test of all of said memory cells.
Claim 7
Dependent Claim
24 words
An erasable non-volatile semiconductor memory device as claimed in claim 4, wherein said cell transistors are constituted by floating gate avalanche injection MIS transistors.
Claim 8
Dependent Claim
68 words
An erasable non-volatile semiconductor memory device as claimed in claim 4, wherein the first and second bit lines are provided between each of two cell transistors of said memory cell and said differential type detection circuit, and the switching processes between said first and second bit lines and said power supply means and the ground are controlled by switching elements controlled during a test of said memory cells.
Claim 9
Dependent Claim
157 words
An erasable non-volatile semiconductor memory device having a plurality of erasable non-volatile memory cells each comprising two cell transistors, the write statuses of which are inverted, and detecting the write status of each of said memory cells by a differential type detection circuit through first and second bit lines connected respectively to said two cell transistors of said memory cell, to thereby read out the contents of said memory cell, wherein said erasable non-volatile semiconductor memory device comprises: an all cell transistor write means for writing all of said cell transistors constituting a plurality of said memory cells; a first test means for connecting said second bit line to the ground to carry out a test of a first write level; and a second test means for connecting said first bit line to the ground to carry out a test of a second write level, to thereby execute a read/write test of all of said memory cells.
Claim 10
Dependent Claim
157 words
An erasable non-volatile semiconductor memory device having a plurality of erasable non-volatile memory cells each comprising two cell transistors, the write statuses of which are inverted, and detecting the write status of each of said memory cells by a differential type detection circuit through first and second bit lines connected respectively to said two cell transistors of said memory cell, to thereby read out the contents of said memory cell, wherein said erasable non-volatile semiconductor memory device comprises: an all cell transistor write means for writing all of said cell transistors constituting a plurality of said memory cells; a first test means for connecting said second bit line to the ground to carry out a test of a first write level; and a second test means for connecting said first bit line to the ground to carry out a test of a second write level, to thereby execute a read/write test of all of said memory cells.
Claim 11
Dependent Claim
24 words
An erasable non-volatile semiconductor memory device as claimed in claim 7, wherein said cell transistors are constituted by floating gate avalanche injection MIS transistors.
Claim 12
Dependent Claim
68 words
An erasable non-volatile semiconductor memory device as claimed in claim 7, wherein said first and second bit lines are provided between each of two cell transistors of said memory cell and said differential type detection circuit, and the switching processes between said first and second bit lines and said power supply means and the ground are controlled by switching elements controlled during a test of said memory cells.
Claim 13
Dependent Claim
271 words
A read/write test method of an erasable non-volatile semiconductor memory device, having a plurality of erasable non-volatile memory cells each comprising two cell transistors, the write statuses of which are inverted, and detecting the write status of each of said memory cells by a differential type detection circuit through first and second bit lines connected respectively to said two cell transistors of said memory cell to thereby read out the contents of said memory cell, wherein said read/write test method comprises the steps of: erasing all of said cell transistors constituting a plurality of said memory cells; cutting off said first bit line connected to one of said cell transistors from said differential type detection circuit, and connecting said second bit line connected to the other of said cell transistors of said memory cell to said differential type detection circuit to carry out a test of a first write level; cutting off said second bit line from said differential type detection circuit, and connecting said first bit line to said differential type detection circuit to carry out a test of a second write level; writing all of said cell transistors constituting a plurality of said memory cells; connecting said second bit line to the ground, and connecting said first bit line to said differential type detection circuit to carry out a test of the first write level; and connecting said first bit line to the ground, and connecting said second bit line to said differential type detection circuit to carry out a test of the second write level, so that the read/write test of all of said memory cells is executed.
Claim 14
Dependent Claim
271 words
A read/write test method of an erasable non-volatile semiconductor memory device, having a plurality of erasable non-volatile memory cells each comprising two cell transistors, the write statuses of which are inverted, and detecting the write status of each of said memory cells by a differential type detection circuit through first and second bit lines connected respectively to said two cell transistors of said memory cell to thereby read out the contents of said memory cell, wherein said read/write test method comprises the steps of: erasing all of said cell transistors constituting a plurality of said memory cells; cutting off said first bit line connected to one of said cell transistors from said differential type detection circuit, and connecting said second bit line connected to the other of said cell transistors of said memory cell to said differential type detection circuit to carry out a test of a first write level; cutting off said second bit line from said differential type detection circuit, and connecting said first bit line to said differential type detection circuit to carry out a test of a second write level; writing all of said cell transistors constituting a plurality of said memory cells; connecting said second bit line to the ground, and connecting said first bit line to said differential type detection circuit to carry out a test of the first write level; and connecting said first bit line to the ground, and connecting said second bit line to said differential type detection circuit to carry out a test of the second write level, so that the read/write test of all of said memory cells is executed.
Claim 15
Dependent Claim
215 words
A read/write test method of an erasable non-volatile semiconductor memory device, having a plurality of erasable non-volatile memory cells each comprising two cell transistors, the write statuses of which are inverted, and detecting the write status of each of said memory cells by a differential type detection circuit through first and second bit lines connected respectively to said two cell transistors of said memory cell to thereby read out the contents of said memory cell, wherein said read/write test method comprises the steps of: erasing all of said cell transistors constituting a plurality of said memory cells; connecting said first bit line connected to one of said cell transistors to a power supply means to carry out a test of a first write level; connecting said second bit line connected to the other of said cell transistors to said power supply means to carry out a test of a second write level; writing all of said cell transistors constituting a plurality of said memory cells; connecting said second bit line to the ground to carry out a test of the first write level; and connecting said first bit line to the ground to carry out a test of the second write level, so that the read/write test of all of said memory cells is executed.
Claim 16
Dependent Claim
215 words
A read/write test method of an erasable non-volatile semiconductor memory device, having a plurality of erasable non-volatile memory cells each comprising two cell transistors, the write statuses of which are inverted, and detecting the write status of each of said memory cells by a differential type detection circuit through first and second bit lines connected respectively to said two cell transistors of said memory cell to thereby read out the contents of said memory cell, wherein said read/write test method comprises the steps of: erasing all of said cell transistors constituting a plurality of said memory cells; connecting said first bit line connected to one of said cell transistors to a power supply means to carry out a test of a first write level; connecting said second bit line connected to the other of said cell transistors to said power supply means to carry out a test of a second write level; writing all of said cell transistors constituting a plurality of said memory cells; connecting said second bit line to the ground to carry out a test of the first write level; and connecting said first bit line to the ground to carry out a test of the second write level, so that the read/write test of all of said memory cells is executed.
Claim 17
Dependent Claim
146 words
A read/write test method of an erasable non-volatile semiconductor memory device having a plurality of erasable non-volatile memory cells each comprising two cell transistors, the write statuses of which are inverted, and detecting the write status of each of said memory cells by a differential type detection circuit through first and second bit lines connected respectively to said two cell transistors of said memory cell, to thereby read out the contents of said memory cell, wherein said read/write test method comprises the steps of: writing all of said cell transistors constituting a plurality of said memory cells; connecting said second bit line to the ground to carry out a test of a first write level; and connecting said first bit line to the ground to carry out a test of a second write level, to thereby execute a read/write test of all of said memory cells.
Claim 18
Dependent Claim
146 words
A read/write test method of an erasable non-volatile semiconductor memory device having a plurality of erasable non-volatile memory cells each comprising two cell transistors, the write statuses of which are inverted, and detecting the write status of each of said memory cells by a differential type detection circuit through first and second bit lines connected respectively to said two cell transistors of said memory cell, to thereby read out the contents of said memory cell, wherein said read/write test method comprises the steps of: writing all of said cell transistors constituting a plurality of said memory cells; connecting said second bit line to the ground to carry out a test of a first write level; and connecting said first bit line to the ground to carry out a test of a second write level, to thereby execute a read/write test of all of said memory cells.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-08-16 | 1997-02-15 | 1997-08-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-08-16 | 2001-02-15 | 2001-08-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-08-16 | 2005-02-15 | 2005-08-17 | $7700.00 | Window Closed / Lapsed |