US5239561A
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US
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Phase error processor
Assignee: National Semiconductor Corp
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Filing: 1991-07-15
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Granted: 1993-08-24
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Expires: 2011-07-15
Abstract
Abstract A phase error processor interfaces a proportionate phase detector to a digital loop filter in a high frequency phase-locked loop (PLL). The PLL receives a high frequency stream of NRZI encoded data, which contains a variable density of data signal transitions. A phase detector in the PLL generates proportionate phase error information in the form of a phase error pulse signal PD1 and a reference pulse signal PD2 for each data transition in the incoming data s The phase error processor, using a "decimation" technique, integrates the proportionate phase error information from just one pair of adjacent positive and negative data transitions during each period of N clock cycles if the number of input data transitions which occur during that time period exceeds the expected minimum, otherwise the phase error processor passes no phase error information. The selection of window width is based on the coding scheme of the incoming data stream. The integrated information is converted by the phase error processor once during each N-clock cycle period into a one-bit Up/Down signal that is then used to either advance or retard the output phase of the PLL's digitally controlled oscillator. The phase error processor also detects when the density of edges in the incoming data stream falls below a minimum allowed level, and generates a "data valid" signal indicating whether the Up/Down signal are valid.
Inventors
- 👤 Hee Wong
- 👤 Tsun-Kit Chin
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 17:26
CPC Classifications
H; H04; H04L; H04L7/00; H03; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/099; H03L7/0991; H03L7/085; H04L7/02; H04L7/033
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
129 words
A phase error processor for use in a data recovery circuit, comprising: a time slot decoder which receives a cyclic clock signal and generates timing signals defining a data processing window of N clock cycles, where N is a positive integer; an integration circuit, coupled to said time slot decoder, which receives proportionate phase error information from a phase detector for each data transition in a data signal, said integration circuit integrating said proportionate phase error information for a predetermined number of data transitions during each data processing window; and comparator means, coupled to said integration circuit and said time slot decoder, for comparing said integrated proportionate phase error information with a reference signal and generating an Up/Down signal in accordance with said comparison once each data processing window.
Claim 2
Dependent Claim
129 words
A phase error processor for use in a data recovery circuit, comprising: a time slot decoder which receives a cyclic clock signal and generates timing signals defining a data processing window of N clock cycles, where N is a positive integer; an integration circuit, coupled to said time slot decoder, which receives proportionate phase error information from a phase detector for each data transition in a data signal, said integration circuit integrating said proportionate phase error information for a predetermined number of data transitions during each data processing window; and comparator means, coupled to said integration circuit and said time slot decoder, for comparing said integrated proportionate phase error information with a reference signal and generating an Up/Down signal in accordance with said comparison once each data processing window.
Claim 3
Dependent Claim
36 words
The phase error processor of claim 1, wherein said integration circuit integrates said proportionate phase error information for a pair of adjacent positive and negative data transitions in said data signal during each data processing window.
Claim 4
Dependent Claim
38 words
The phase error processor of claim 1, wherein said integration circuit integrates said proportionate phase error information for at least one pair of adjacent positive and negative data transitions in said data signal during each data processing window.
Claim 5
Dependent Claim
33 words
The phase error processor of claim 1, including means for generating a data valid signal whenever said data signal contains at least a predefined number of data transitions during a data processing window.
Claim 6
Dependent Claim
63 words
The phase error processor of claim 1, including a gating circuit that filters the proportionate phase error information received by said integration circuit from said phase detector, said gating circuit allowing no more than a predefined number of proportionate phase error information signals, from a corresponding number of data signal transitions, to propagate to said integration circuit during each said data processing window.
Claim 7
Dependent Claim
34 words
The phase error processor of claim 1, said integration circuit including means for dumping said integrated phase error information once per data processing window so as to prepare for integrating additional phase error information.
Claim 8
Dependent Claim
224 words
A phase error processor for use in a data recovery circuit, comprising: a time slot decoder that receives a cyclic clock signal and generates timing signals defining a data processing window of N clock cycles, where N is a positive integer; a differential integration circuit, coupled to said time slot decoder, which receives proportionate phase error information from a phase detector for each data transition in a data signal; said received proportionate phase error information including a first pulse signal having a pulse width TW1 corresponding to phase error between each data transition in said data signal and a PLL clock signal, and a second pulse signal having a width TW2 that corresponds to a predefined portion of said PLL clock signal's cycle, wherein the difference in the pulse widths of said first and second pulse signals is proportional to said phase error between said data signal and said PLL clock signal; said integration circuit including first integrating means for integrating a plurality of said first pulse signals and second integrating means for integrating a corresponding plurality of said second signals during each data processing window; and comparator means, coupled to said integration circuit and said time slot decoder, for comparing said first and second integrated pulse signals, and for generating an Up/Down signal in accordance with said comparison once each data processing window.
Claim 9
Dependent Claim
224 words
A phase error processor for use in a data recovery circuit, comprising: a time slot decoder that receives a cyclic clock signal and generates timing signals defining a data processing window of N clock cycles, where N is a positive integer; a differential integration circuit, coupled to said time slot decoder, which receives proportionate phase error information from a phase detector for each data transition in a data signal; said received proportionate phase error information including a first pulse signal having a pulse width TW1 corresponding to phase error between each data transition in said data signal and a PLL clock signal, and a second pulse signal having a width TW2 that corresponds to a predefined portion of said PLL clock signal's cycle, wherein the difference in the pulse widths of said first and second pulse signals is proportional to said phase error between said data signal and said PLL clock signal; said integration circuit including first integrating means for integrating a plurality of said first pulse signals and second integrating means for integrating a corresponding plurality of said second signals during each data processing window; and comparator means, coupled to said integration circuit and said time slot decoder, for comparing said first and second integrated pulse signals, and for generating an Up/Down signal in accordance with said comparison once each data processing window.
Claim 10
Dependent Claim
94 words
The phase error processor of claim 7, said data signal having alternating positive and negative transitions; said first integrating means integrating at least two successive ones of said first pulse signals, corresponding to successive positive and negative transitions in said data signal; said second integrating means integrating successive ones of said second pulse signals corresponding to the first pulse signals integrated by said first integrating means; and said comparator means, coupled to said first and second integrating means, generating an Up/Down signal corresponding to the difference between said integrated first and second pulse signals.
Claim 11
Dependent Claim
33 words
The phase error processor of claim 7, including means for generating a data valid signal whenever said data signal contains at least a predefined number of data transitions during a data processing window.
Claim 12
Dependent Claim
63 words
The phase error processor of claim 7, including a gating circuit that filters the proportionate phase error information received by said integration circuit from said phase detector, said gating circuit allowing no more than a predefined number of proportionate phase error information signals, from a corresponding number of data signal transitions, to propagate to said integration circuit during each said data processing window.
Claim 13
Dependent Claim
34 words
The phase error processor of claim 7, said integration circuit including means for dumping said integrated phase error information once per data processing window so as to prepare for integrating additional phase error information.
Claim 14
Dependent Claim
199 words
A phase error processor for use in a data recovery circuit, comprising: a time slot decoder that receives a cyclic clock signal and generates timing signals defining a data processing window of N clock cycles, where N is a positive integer; a gating circuit that receives proportionate phase error information from a phase detector for each data transistion in a data signal; said received proportionate phase error information including a first pulse signal having a pulse width TW1 corresponding to phase error between each data transition in said data signal and a PLL clock signal, and a second pulse signal having a width TW2 that corresponds to a predefined portion of said PLL clock signal's cycle, wherein the difference in the pulse widths of said first and second pulse signals is proportional to said phase error between said data signal and said PLL clock signal; said gating circuit allowing a predefined number of said first and second pulse signals, from a corresponding number of data signal transitions, to propagate through said gating circuit during each said data processing window; wherein said gating circuit uses identical circuits for gating said first pulse signal and for gating said second pulse signal.
Claim 15
Dependent Claim
199 words
A phase error processor for use in a data recovery circuit, comprising: a time slot decoder that receives a cyclic clock signal and generates timing signals defining a data processing window of N clock cycles, where N is a positive integer; a gating circuit that receives proportionate phase error information from a phase detector for each data transistion in a data signal; said received proportionate phase error information including a first pulse signal having a pulse width TW1 corresponding to phase error between each data transition in said data signal and a PLL clock signal, and a second pulse signal having a width TW2 that corresponds to a predefined portion of said PLL clock signal's cycle, wherein the difference in the pulse widths of said first and second pulse signals is proportional to said phase error between said data signal and said PLL clock signal; said gating circuit allowing a predefined number of said first and second pulse signals, from a corresponding number of data signal transitions, to propagate through said gating circuit during each said data processing window; wherein said gating circuit uses identical circuits for gating said first pulse signal and for gating said second pulse signal.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-08-23 | 1997-02-22 | 1997-08-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-08-23 | 2001-02-22 | 2001-08-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-08-23 | 2005-02-22 | 2005-08-24 | $7700.00 | Window Closed / Lapsed |